About us

default image

RTLery logic design library and design services

RTLery website content is written and maintained by highly experienced logic design engineers with over 15 years of experience in all aspects of the chip design flow. The team has vast experience, in hand on design of complex logical blocks, device interface, chip integrations, block and chip level verification, chip timing closure, DFT,  floor-planning  and more. Our team’s managerial experience in design team management and chip project management for the largest chip maker companies, as well as few fabless start-up companies, enables us to understand the challenges of chip design projects and offer solutions for focusing design teams on their core differentiating tasks while increasing their productivity and lowering the design risks.

Read More

Our Mission

1
Provide excellent components

provide logic designers with generic components for the most used design structures, allowing the designer to focus on the architectural aspect of the block

2
Provide specialized design service

Provide professional design service for the complex portions of clocking, and physical interfaces where timing and logic design disciplines are required in order to produce a robust design

3
Provide synthesis and timing service

Leverage our experience in helping design teams prepare the design and timing constraints for backend implementation, bridging the gap between place and route view and the logical requirements of the device architecture


Our Philosophy

RTLery is focused on assisting design team accomplish better results in shorter time
The RTLery website provides RTL design engineers with verified and well documented code examples for many of the generic components used in different designs across the semiconductor industry ranging from the simple FIFO to the most complicated algorithms and functions.

The goal of RTLery is to make knowledge accumulation faster and enable the designer to concentrate on the design architectural challenges and reach his target functionality faster. Using pre-verified generic components will save debugging time and reduce overall design and verification effort.


Our Skills

Logic Design 80%
Synthesis and constraints 70%
Formal equivalence 60%
Gate level simulation 90%
clocking and reset design 90%

Our Team

  • lead engineer

    Amnon Parnass

    Expert designer for ASIC top level, PLLs integration, clocking and reset schemes in few ASIC projects.