How to design

  • how to design a round robin arbiter

    The logic design of an efficient and fast round robin arbiter in Verilog or any other HDL language relies on the capability to find the next requestor to grant without losing cycles and with minimal logical stages.

  • how to design a weighted round robin arbiter

    When coming to the task of designing a weighted round arbiter in Verilog or other HDL languages, we need to consider the timing, power and area of the design, as well as the weighted arbitration algorithm.

  • how to design an on-chip clock frequency measurement

    This article presents the logic behind the design and implementation of a clock frequency or period measurement block. The article walks you through the principles used in designing multiple clock blocks, listing the potential pitfalls and offers a clear and practical solution anyone can implement.

  • How to design an inter-block connectivity FIFO

    The purpose of an inter-block connectivity block is to facilitate full-chip integration by simplifying the timing constraints and logical interface of block interconnects. The advantages of using a clean and generic design for interfacing between blocks within a device are evident during top level timing integration.