Fullchip design

  • Ring oscillator performance monitor

    The process, voltage and temperature (PVT) of a silicon device has high impact on its performance. Measuring the performance of a circuit and the variation across a device is essential for device characterization and screening for operational frequency.

  • how to design an on-chip clock frequency measurement

    This article presents the logic behind the design and implementation of a clock frequency or period measurement block. The article walks you through the principles used in designing multiple clock blocks, listing the potential pitfalls and offers a clear and practical solution anyone can implement.

  • FullChip physical block diagram

    The process of designing an ASIC top level requires the designer to start from functional block diagram of a chip, typically produced by the chip architecture team based the chip functionality and produces a physical block diagram.

  • Asic top level in one week - case study

    The purpose of this customer case study is to present a situation where a first time ASIC design team managed to develop a fully functional top level with I/O, multiple PLLs, clock and reset distribution logic and power-up sequence in 1 week using RTLery library components. The customer used RTLery’s top level building blocks component, reference implementations as well as RTLery’s customization service to design and connect all the required top level functionality of the device and reached operational full chip integration in a very short period of time, enabling verification and backend efforts to begin.