The purpose of this customer case study is to present a situation where a first time ASIC design team managed to develop a fully functional top level with I/O, multiple PLLs, clock and reset distribution logic and power-up sequence in 1 week using RTLery library components. The customer used RTLery’s top level building blocks component, reference implementations as well as RTLery’s customization service to design and connect all the required top level functionality of the device and reached operational full chip integration in a very short period of time, enabling verification and backend efforts to begin.
Integrating multiple PLLs into an ASIC device requires careful planning and strict coding style to handle all clock domain crossings. In a multiple PLL design, the first impression may bring a designer to think the PLLs are independent and therefore the initialization sequence would function independently. This observation is in most cases wrong, leading to re-design and patching.