Methodology

  • FullChip physical block diagram

    The process of designing an ASIC top level requires the designer to start from functional block diagram of a chip, typically produced by the chip architecture team based the chip functionality and produces a physical block diagram.

  • Multiple PLL integration - doing it right

    Integrating multiple PLLs into an ASIC device requires careful planning and strict coding style to handle all clock domain crossings. In a multiple PLL design, the first impression may bring a designer to think the PLLs are independent and therefore the initialization sequence would function independently. This observation is in most cases wrong, leading to re-design and patching.

  • FPGA to ASIC conversion

    Design teams choosing to walk the treacherous path from FPGA to ASIC face many hardships.  The main problems come from the missing knowledge in different aspects of clocking, reset, PLLs, physical design partitioning, floor-planning and more.  The design team used to the benefits of the FPGA protected world, where all marginally complicated elements come as macros and mega blocks.

  • Component based logic design

    The front end of ASIC or FPGA design flow consists of definition, requirements, architecture and logic design. In recent attempts to shorten the time to market for ASIC products, there is a significant improvement in this area coming from high level synthesis and system level engineering methodologies, but those will only become main stream in the future.