Asic top level in one week - case study

clocking and reset block diagram


The purpose of this customer case study is to present a situation where a first time ASIC design team managed to develop a fully functional top level with I/O, multiple PLLs, clock and reset distribution logic and power-up sequence in 1 week using RTLery library components. The customer used RTLery’s top level building blocks component, reference implementations as well as RTLery’s customization service to design and connect all the required top level functionality of the device and reached operational full chip integration in a very short period of time, enabling verification and backend efforts to begin.


The customer is a video imaging devices manufacturer that has relied on FPGA for the previous products and is on the process of moving to ASIC for the purpose of power and size reduction. The device was to be designed for TSMC 65nm process and contains 3 major clock domains and several external device interfaces, some using protocols such as I2C and SPI while others are using device proprietary clocking schemes and data sampling timing definitions. The device interfaces to an external system controller processor that governs the device configuration, initialization and management, connecting through an asynchronous interface.

Problems and challenges

As FPGA devices contain built-in macros for handling PLL, clock distribution and reset, the team did not have the required know-how to design those parts for an ASIC and searched for external solutions. The device contains multiple clock domains and requirements for switching clock source for specific elements during the device operation. The design contains 3 PLLs and requires a powerup sequence that is driven by an external system controller. The device uses functional video clocks of low frequency (1 to 50Mhz) with multiple possible frequencies within that range. The required frequency is below the dynamic range of most of-the-shelf PLLs in latest process nodes resulting in a requirement for a clock divider for the video clock source PLLs capable of generating slower clocks with division ratios that are not the binary 2, 4, 8.

The reset of the device with all 3 frequency domains is based on a single source asynchronous reset signal that is propagated to the entire device from a single source.

The project timeline was very short, leaving restricted to finalize the device top level so initial floor-planning activity can begin.

To meet the design requirements in the allocated timeframe and enable smooth physical design activity there was a need for a solution to the design challenges which can be implemented in a short period and provide the necessary high confidence that will enable physical design start.


The solution offered by RTLery was to use the library of top level design components in order to speed up the design process and lower the risks. Library components were used for the tree major challenges:

1.    PLL integration, clock frequency division, reset synchronization and powerup sequence.

2.    Clock switching for internal logic.

3.    Asynchronous FIFO synchronizers.

In addition to the pre-designed components, RTLery offered to customize the PLL integration for the selected PLL and modify the powerup sequence logic to meet the specific design requirements.

PLL and clock division

RTLery offers design and integration service of a PLL, a power-up sequencer and a glitch free clock multiplexer allowing a safe switch from PLL bypass mode to functional mode. For this design RTLery performed a replacement of a generic PLL in the reference design with the device PLL according to the PLL specification. The PLL initialization sequence parameters of the component were set according to the requirements of the specific PLL.

The same PLL initialization sequence was used for all 3 PLLs of the device, allowing for a re-use of the same initialization sequence component.

a clock divider from the RTLery design core library was added on the video clock PLLs output, providing added division of up to 1/32, making it possible to reach frequencies like 3,18,25,27Mhz using the available PLL. The initialization of the divider was added to the PLL powerup sequence.

In order to provide feedback to the software regarding PLL initialization and configuration, the RTLery library an on-chip frequency measurement counter was added to the video clock PLL and divider outputs. The frequency measurement allows the software to probe the current frequency of the PLL and verify the PLL and divider configuration. This feature enables easier device bring-up and enables simple testing and calibration.

Reset synchronization and propagation

In terms of reset, RTLery library reset and powerup sequencer was used for synchronizing the external reset to the internal device clock domain and filter unintended reset signal changes. On the core side, the power-up sequence enabled a safe de-assertion of the reset signal to all the device clock domains. This operation became possible by using the library glitch free clock multiplexer component feature that allows the clocks to be stopped.  The way to de-assert the reset for multiple asynchronous clock domains where the same reset signal is connected to all clock domains within the block is to stop the clocks while de-asserting the reset. This will prevent any timing issues between the reset and clock signals and allow for a safe reset de-assertion.

clock and reset initialization block diagram

Clock switching for memory array initialization

The device contains large memory array lookup tables that require initialization and maintenance during the device operation. The requirement for fast update of the tables from the external system controller forces the designers to use a faster clock to initialize the tables instead of the functional video clock. Changing the clock source for an embedded memory array within the device requires caution, no to create clock glitches and corrupt the data in the memory during the switch. The solution offered by RTLery was to use the library glitch free clock multiplexer to safely switch between the two clocks without glitches. The integration of the component allowed for safe switching on 14 different locations within the device, saving effort and risks.

Memory access mux using clock switch component


Asynchronous FIFO synchronization

One of the device external interfaces is a connection to a device that sends data in a source synchronous manner where the data is aligned to an incoming clock. The external device receives its clock from the chip so both clocks are frequency locked. In order to synchronize the incoming data, the RTLery library asynchronous FIFO synchronizer was used. The synchronizer loading side was connected to the external clock, sampling incoming external device data. The synchronizer extracting side was connected to an internal version of the external device clock, used for clocking the downstream processing blocks. This arrangement enables the device to use internally generated clock for its processing pipe while keeping the external device clocked according to its requirements. The asynchronous FIFO was used in several other locations in the device, allowing for lesser dependency between different clocks and more physical implementation flexibility.


asynchronous FIFO clocking diagram


The most valuable result from the usage of RTLery components for this device was a fully functional top level, designed in only 1 week. Using the RTLery power-up sequence service and reference design as a starting point for implementing the specific design requirements enabled quick modifications while keeping the basic power-up sequence functionality. RTLery customization and PLL integration service, enabled a smooth integration of the device selected PLL and allowed the design team to meet all design specifications in terms of reset propagation, clock frequencies and clock domains with minimal risk.

The usage of glitch free clock multiplexing component resulted in streamlining of the design effort around large memory tables, where all designers used the same logic reducing bug risks in this sensitive logic.


The component based design method used in this device top level functionality enabled very fast integration of PLLs and reset logic. The usage of RTLery components can greatly improve design time while simultaneously reducing risk. The simplicity of integration and clear specification and documentation allows every designer to use the components and benefit from the long years of experience invested in them. The lessons of this device design can be leveraged for other products where the designers can concentrate on the new and innovative parts of their chip, leaving the standard and re-usable parts of the code to component libraries such as RTLery website. Future RTLery library users will have access to several context based collections of components in different subjects such as arbiters, inter-block connectivity, top level CSR interconnect, external interfaces and more.

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