The front end of ASIC or FPGA design flow consists of definition, requirements, architecture and logic design. In recent attempts to shorten the time to market for ASIC products, there is a significant improvement in this area coming from high level synthesis and system level engineering methodologies, but those will only become main stream in the future.
In the past, significant breakthroughs in electronics design productivity were achieved through changes in the abstraction level of the design. Using a higher abstraction level HDL language and synthesis tools enabled a leap forward in design sizes and engineer
ing capacities. Looks like the next step towards synthesis of even higher level languages such as C will take longer than expected as conflicting requirements for power and area make it almost impossible for mainstream designs.
When tools cannot supply the answer, we need to turn to the next best thing, methodology. Methodology is a key component in many parts of the chip design flow but in the logic design domain, methodologies are currently limited to technical aspects such as coding style or Lint issues and only lately some tools address clock domain crossing and other design structures.
The solution for better logic design results therefore lies with a methodology that will enable higher level of abstraction. We need a methodology that integrates design intent definition coherency and facilitates faster verification. The way to do it is by using a compon
ent based design methodology. This methodology is well known and widely used in the software industry and can be used also for chip design. The usage of IP is prevalent but this only applies to the larger blocks and specially complicated functionalities.
Using a component based design methodology for the low level functions will have significant impact on the design quality, the speed of execution and especially the number of bugs. Adopting a methodology of component based design from the micro-architecture stage; through the coding itself all the way to the verification facilitates design intent understanding, simplifies connectivity and enables verification constructs re-use.
So what components are the basic blocks to be used in this methodology? The components are FIFOs of different kinds, Arbiters, inter-block connectivity modules, clocking elements and more. Basically any block that is worth re-using is a good candidate for being a basic component for this purpose.
How is this method used? The design starts at the micro-architecture level where the components are used in every possible place they fit. Mapping the intended specification of the block into pre-designed and readily available components will definitely reduce the overall design time and greatly improve quality. Naturally some of the logic must be specific to the block functionality but getting this part right would ensure the block performs its design intent.
The most significant impact of using this methodology in block design is in the verification. The advantage of using pre-verified components is huge, debug and initial bring up are easier and faster. If the components are used for block interfaces, the block level verification may even get easier as the stubs can also be re-used.
So how do we start using this methodology? The first step would be to get the basic components either from previous designs, through an intentional process of organized re-use or by outsourcing a basic components library containing most basic building blocks.
The RTLery library offers basic component library where you can find many of the designs needed for standard block level designs and start using the component based methodology in your next chip. The results would definitely be faster design cycle, easier verification and belter overall quality of results.