Design teams choosing to walk the treacherous path from FPGA to ASIC face many hardships. The main problems come from the missing knowledge in different aspects of clocking, reset, PLLs, physical design partitioning, floor-planning and more. The design team used to the benefits of the FPGA protected world, where all marginally complicated elements come as macros and mega blocks. The typical FPGA designer does not have to deal with PLL integration, power-up sequences, reset propagation, I/Os and most external interfaces.
There are several options to overcome this obvious gap of knowledge and experience. The obvious strait forward solution would be to gain the experience through hiring experienced engineers capable of designing those delicate pieces of the ASIC, building the capabilities for next rounds but also increases the long term expenses. Another suitable solution would be to outsource the design task of the clocking and reset handling blocks resulting in no knowledge accumulation and a significant loss of control over this very sensitive logic. A third option is to use pre-designed building blocks from a third party with some customizations service, this way the risk is reduced while keeping the methodology close to the native FPGA design flow. Instead of using mega blocks from an FPGA vendor, a library of components, specifically designed to support full chip integration, clock and reset distribution and power-up sequence can be used.
The availability of open code components enables easy adoption of the components to the specific needs and easy addition of features. Therefore, the right way to address the FPGA to ASIC conversion knowledge and experience gap is to get the required blocks for the ASIC in much the same way as for the FPGA, by using a library of components specifically designed to address ASIC top level design.
Although it seem that the top level of each ASIC is different, the reality is that most ASIC designs need to sample reset from external pins, all of them require some kind of PLL initialization and all have clocking schemes and clock distribution requirements. The design of those blocks is very similar in most cases and can be easily customized for specific requirements.
Addressing the FPGA to ASIC conversion task through a component based design methodology most resembles the original FPGA design line of thinking and will fit perfectly with the team’s concept of designing a device. Using pre-verified and pre-designed components shortens the design cycle, reduces risks and results in streamlining of the full-chip integration.
RTLery web based component library offers a collection of pre-designed and pre-verified components for ASIC top level clocking, power-up sequence and reset propagation delivered with full documentation and optional customization support. Using this library can significantly reduce the complexity for first-time-ASIC teams, allowing them to use more familiar methods for their first design and avoid some of the pitfalls waiting for them in this conversion.