Integrating multiple PLLs into an ASIC device requires careful planning and strict coding style to handle all clock domain crossings. In a multiple PLL design, the first impression may bring a designer to think the PLLs are independent and therefore the initialization sequence would function independently. This observation is in most cases wrong, leading to re-design and patching.
To arrive at a good definition for the PLL integration we need to consider the following aspects carefully:
- What is the PLL configuration method? Does every PLL have a constant configuration? Is there a need for software to configure the PLL divide ratios during power-up? How will the PLLs configuration be set?
- What is the reset sequence? Is there a single reset signal for all PLL clock domains? Does the device require a separate reset per clock domain?
- What is the role of each PLL in the overall power-up sequence? Is one PLL required before the others can be initialized?
Considering the above questions would enable you to figure out the best way to handle this multiple PLL power-up sequence. Let’s try to work through some examples and find out the correct solution for each case.
The first example would be a case where 3 PLLs are used in the device. The first PLL powers the device central control logic and the external CPU interface. The other two PLLs are clocking the functional blocks and require external CPU configuration to determine the frequency per the specific application and operation mode. The reset signal to the functional blocks is shared for all clock domains, requiring the reset de-assertion to be executed when all clocks are ready. So how do we approach this set of requirements and come up with the best solution?
Naturally, we need to sequence the reset in two stages, the first one would release the external CPU interface so it can configure the other PLLs. On the other side of the reset, the blocks need to receive it’s de-assertion at the same time, so hardware needs to synchronize the reset de-assertions for the 3 clock domains. The main PLL, driving the central control clock would therefore be initialized first, starting at the external reset de-assertion. Once the main PLL is ready and locked, the power-up sequence would de-assert the reset to the external CPU interface block, enabling the external CPU to write the other PLLs configurations and start their initialization sequence.
The second stage of reset de-assertion waits for the PLLs to be locked. When the two PLLs are fully initialized by the external CPU and are locked, the hardware would again take over and release the reset to the rest of the device.
Of course, the external reset pin requires strict synchronization, the configuration word of the main PLL needs to be sampled correctly and all DFT aspects of the power-up sequence need to be carefully considered.
One more thing that requires special attention is the synchronization between the 3 clock domains. The central control FSM should probably be clocked by the main PLL reference clock, but the control logic for the other PLLs must be clocked by their own reference clock. Therefore, all interaction between the different control blocks must be carefully synchronized. The PLL integration should naturally include clock dividers, to reach lower frequencies if required and switching logic that enables bypass of the PLL.
The second example would be a case of 2 independent clock domains with no specific ordering between them, but both sharing the same reset signal, requiring both clocks to be active when the clock pin is de-asserted.
This case is a bit less complicated, so it would not need any central control logic. The solution in this case is to drive the reset signal into both clock domain and let each PLL initialize at its own time. The reset to the whole device would only be de-asserted once both PLLs are locked and ready.
The attention in this solution would be on robust synchronizers both for the incoming reset signal and the internal device reset signal. Careful control of the bypass path on each of the PLL output path would enable safe power-up every time.
The third case includes multiple PLLs that need to be configured through a very limited serial independent interface that is clocked by an external clock. This scenario requires a single reset sequence to initialize all three PLLs according to the sampled configuration. The PLLs will be initialized in parallel, saving the delay time for PLL lock. The availability of all the configuration information right at the starts, shortens the overall power-up sequence but requires a dedicated interface for driving the configuration information into the device.
As you can see there are no simple and strait forward ways to integrate multiple PLLs into a device and cleanly power them up. Any PLL integration requires strict synchronization between the different clock domains. Carefully designed reset synchronization and robust sequence for power-up and initialization of the different clock domains. The release of the reset signal to the rest of the device is a sensitive issue that needs attention and heavily depends on the handling of the clock domain crossings at the different block levels.
On top of all those aspect, you must consider DFT aspects, clocking of the device internals during the power-up sequence and debug options such as PLL bypassing. And just to be sure you have it the right logic; you may want the capability to measure the frequency on the chip so software can decide for itself if it has the right configuration. You may also try to facilitate easier testing on an ATE by driving the PLL outputs to a pin in some test mode, allowing the tester to check the frequency.
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