In some of today’s power-hungry devices, the issue of peak power is significant, posing a major challenge to chip power grid design as well as the device packaging. Synchronous logic, typically has a power peak at the time of the clock rise and since the clock is balanced throughout the device, it happens all across the device at the same time. Highly congested devices typically do not have sufficient capacitance to handle the peak current rush.
So what else can you do to prevent this peak current rush?
A good way to do it is by shifting the clocks for different parts of the design relative to each other, so the peak current does not occur simultaneously all over the device.
Naturally you will have to handle the asynchronous nature of communication between different parts of the design that receive clocks that are shifted using asynchronous FIFO or any other mechanism. Once you get the synchronization issues solved, you will still need to handle the clock shifting, keeping the clocks away from each other at all process corners as well as different voltage and temperature scenarios. Doing that will ensure you get a manageable peak power where demand for current is spread over longer period of time and not concentrated around the clock edge event.
You can simply use few buffers to shift the clock, but what would be the result in different process corners? How will the clock phase look like when temperature changes? How can you ensure that the desired phase shift remains when you change the frequency?
The best way to solve all those issues is a DLL. A digital DLL can be used for to shift each of the clocks going to the different blocks on the device by a constant portion of the clock, so if you want the clocks to be shifted by 1/8 of the cycle, you can set the delay line for each of the blocks and when you change the frequency, the DLL will keep the same phase shift between the clocks for optimal peak power reduction.
The DLL to use is a digital master-slave DLL. The master would measure the clock cycle continuously and a slave per block can be used to shift the clock by the desired ratio. So if you program the slaves to delay the clock by 1/8, 2/8, 3/8, 4/8…, you will have the same shift, in different frequencies and PVT corners.
The digital DLL has low cell count, low power consumption and relatively low complexity of physical implementation. It is easily convertible to different process nodes and libraries.
The use of a DLL for the purpose controlling the peak power of a chip is not a typical use of a DLL but is one of the best ways to reduce peak power and use this flexible technology in yet another application of chip clocking design.
RTLery website offers a phase shift DLL design that can be used for this application. The available DLL also includes programmable offset for each of the delay lines, so any constant skews induced by clock tree synthesis can be cancelled out. The DLL comes with detailed physical design instruction so any backend engineer can properly place and route the DLL and keep its accurate phase shifting.