Company profile details

RTLery company profile

Our Team

RTLery website content is written and maintained by highly experienced logic design engineers with over 15 years of experience in all aspects of the chip design flow. The team has vast experience, in hand on design of complex logical blocks, device interface, chip integrations, block and chip level verification, chip timing closure, DFT,  floor-planning  and more. Our team’s managerial experience in design team management and chip project management for the largest chip maker companies, as well as few fabless start-up companies, enables us to understand the challenges of chip design projects and offer solutions for focusing design teams on their core differentiating tasks while increasing their productivity and lowering the design risks.

Our Goals and principles is a web based logic design components and code assets library. The library contains a large quantity of components used widely by the chip design community. 

The RTLery website provides RTL design engineers with verified and well documented code examples for many of the generic components used in different designs across the semiconductor industry ranging from the simple FIFO to the most complicated algorithms and functions.

The goal of RTLery is to make knowledge accumulation faster and enable the designer to concentrate on the design architectural challenges and reach his target functionality faster. Using pre-verified generic components will save debugging time and reduce overall design and verification effort.

The RTLery website is designed to address several aspects of logical design practices:

  1. Designer’s limited time is better used focusing on the micro-architectural aspects of the designed block and its overall functionality rather than in the coding of modules, already implemented many times by others.
  2. A library of generic designs can broaden the design team knowledge and facilitate innovative solutions to architectural issues outside the team’s “beaten path” of design.
  3. The method of “Design by example” is the common practice of logic designers and a good reference design which is maintained, documented and verified can significantly reduce the risks of the prevalent “code scavenging” practices.
  4. The implementation of re-use practices within design teams requires significant work to be done upfront when first implementing a module for re-use. This extra effort usually, cannot be justified in the context of schedule and content pressures of chip design projects and therefore is seldom invested. Re-use through an external library, does not require pre-invested effort and the trade-off for using it can be evaluated at the point of usage.
  5. Having an open code library, enables the design engineer to accumulate the knowledge, and improve his design skills by using a safe and proven source of information.
  6. Although code from external source is used, the responsibility to integrate it and the accountability for the quality of the overall block, still lies with the design engineer. The ability to see the actual code and evaluate its qualities and limitations enables the engineer to assume this responsibility and maintain his confidence in the correctness of the block. 


The RTLery website contains many basic components you may need while implementing your design and coding your RTL block. Those basic elements such as FIFOs, decoders, memory wrappers, arbiters and others, would allow you to concentrate on the logic design of the required architecture, leaving the details of the basic components to the RTLery verified components.

In contrast to traditional IP blocks, the RTLery library contains open code, so you have the option to investigate the design, modify it for your specific needs and fix timing issues if they appear when the design is placed and routed. The coding style of the RTLery library is clean and readable, no loops, coding shortcuts, no extensive use of parameters and macros and no unnecessary hierarchies.

Each component will have several examples, implementing different variations suitable for timing requirements, pipelining, reset types and more. You can browse the list and find the one most suitable for you. In case you need some changes, we will be happy to add them to the collection, just use the comments box in the component page to send us a note.


The RTL code on the RTLery website is verified using strict industry standards. You can see the test plan used for verification in the verification tab of each component page. The verification plan includes a list of assumptions, the component assumes on its inputs. The design specification would list the behavior in cases of violation of the input assumptions.

The component verification suite includes a simple testbench and example test, allowing you to run the component in stand-alone mode before you integrate it into your design. Once you have integrated the component into your block, you are bound to save time in the initial compilation and simulation of the block.

Verified components allow you to concentrate the block verification effort on the specifics of the architecture, and micro-architecture saving valuable verification effort.


The designs on the RTLery website are well documented, allowing you to easily understand the implementation details of the component, learn about the underlying principle of its implementation. The detailed knowledge would allow you to make modifications without increasing the risk of bugs.

The documentation includes a detailed block diagram, explanation about the behavior of each input and output, a list of available parameters, a list of input assumptions, timing diagram and more.

The detailed documentation, allow you the designer to learn those component functionalities and understand them, adding to your engineering capabilities and allowing you to expand the range of design task within your reach.

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