• arbiter collection

    Arbiters are design elements targeted for resolving access to shared resources by multiple requestors. The arbitration scheme is typically based on a specific fairness algorithm, allocating each requestor its share of the resource. Arbiters are commonly used in queueing structures of communications and computing designs.

  • Chip clock and reset initialization reference design

    Every ASIC device requires a power-up and initialization sequence, enabling clock to start and reset to be propagated through to all parts of the logic.

  • PPC based weighted work conserving round robin arbiter

    The weight functionality of the round robin arbiter allows each requestor to be granted a number of acknowledges according to its predefined weight, so using this arbiter results in a balanced number of acknowledges for each valid requestor.Round robin arbitration is a scheduling scheme which gives to each requestor its share of using a common resource for a limited time or data elements. The basic algorithm indicates that once a requestor has been serves he would “go around” to the end of the line and be the last to be served again. Using a parallel prefix computation (PPC) speeds up the next granted requestor calculation and improves the circuit timing.

  • glitch free clock multiplexer(mux)

    A clock glitch-free clock multiplexer serves to switch between two asynchronous clocks while protecting downstream logic from clock glitches. The de-glitch clock mux also enables switching when one or both of the clocks are not toggling. This component contains the verified RTL code of the clock switch as well as documentation and timing and physical design instruction.

  • Counter clock divider

    Clock dividers generate slower clocks from a faster reference clock. The simplest clock divider divides a clock frequency by 2 using a single flop and an inverter.  Using the same concept, a counter based clock divider can divide a clock by 2, 4, 8, etc. This component contains RTL Verilog code for clock dividers based on counters.

  • on-chip frequency measurement counter

    The frequency counter can be used for measuring clock rates, of external or internally generated clocks for the many purposes, such as configuration, validation tasks and more. The measured clock is treated as asynchronous to the control clock and any clock frequency relation can be measured.

  • Ring oscillator performance monitor

    This component contains verified RTL Verilog code for a process monitor counter designed to measure the frequency of a ring oscillator output for the purpose of correlating process voltage and temperature between devices and measuring on-chip variation (OCV). A ring oscillator is a device composed of an odd number of logical inverters whose output oscillates between the two logical levels.

  • Interconnect Interface FIFO

    An interface FIFO serves to facilitate chip level integration by providing a full handshake interface between two block that is sampled in both directions. sampling signals in both sending and receiving blocks is a way of reducing the complexity of chip level timing closure.

  • Daisy Chain Control and status bus

    The Control and Status Registers daisy chain connectivity module is to connect a central logic (CPU, DMA controller) to multiple different blocks on a chip using daisy chained bus. The main advantages of daisy chain connectivity are the flexibility of adding new slaves (targets) and the low number of signals running long distance from the central logic to each of the target.

  • Basic FIFO

    FIFO is an acronym for First In, First Out data organization method. FIFOs are widely used in logic design for buffering, queuing and management of rate, priorities and flow control in data applications. A FIFO consists of a read pointer and a write pointer, pointing to entries in a storage array typically, made of flip-flops.

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