• Generic FIFO

    A “generic FIFO” is a reference name to the simple type of synchronous FIFOs, where the memory array is based of flip-flops and the pointers and status (full, empty, almost full etc.) are generated using counters or pointers logic.

  • Memory based FIFO

    A “Memory Based FIFO” is a reference name to the simple type of synchronous FIFOs, where the memory array is based on an embedded memory and the pointers and status (full, empty, almost full etc.) are generated using counters or pointers logic.

  • Gearbox width rate converter FIFO

    A Gearbox FIFO is a component which allows the conversion of data bus width from input to output. Data of W width, written to FIFO can be read, depending on configuration, as W*N or W/N width vectors where N is natural number providing the rate of read and write match the required data bus width change. The component supports three versions of clocking and rate modes.

  • MUltiple FIFO in one memory array

    The Multiple FIFO component is a device which allows hosting multiple FIFO queues of the same depth within a single memory structure. Only one FIFO can be written and read in each clock cycle. Each load or extract request is qualified with the number of the FIFO to which it refers.

  • Weighted round robin multi FIFO queuing

    A queuing structure is based on a set of FIFOs, storing data from different sources and an arbitration mechanism selecting the most suitable requestor according to a predefined algorithm. This component implements a queuing system based on FIFOs and a weighted round robin arbitration scheme.

  • Priority encoder

    Priority encoder is a circuit that converts multiple binary inputs into binary representation of the index of active input bit with the highest priority. Each of input has assigned priority. The least significant bit has the highest priority and the most significant bit the lowest. If more than one input is active at the same time the input having highest priority will take precedence.

  • Event rate counter

    This component contains RTL Verilog code for a rate counter designed to measure the rate of an event. The rate counter can be used for measuring error rates, data rates or any other synchronous event. Rate counters are mostly important for system monitoring and testing, allowing system tuning and validation.

  • Decoders collection

    This component includes the verified RTL Verilog code for some encoders and decoders widely used. The collection includes priority encoders, thermometer decoders, grey code and more linke

  • Asynchronous FIFO synchronizer

    Asynchronous FIFO synchronizer offers a solution for transferring signals and vectors across clock domains without risking meta-stability and coherency problems resulting from partial vector synchronization. The synchronizer is suitable for synchronization of data and control information between asynchronous domain of known data and clock ratio.

  • Linked list queuing

    A linked-list based queuing system manages the enqueue, dequeue and arbitration actions for a multiple queue structure implemented using a single embedded SRAM memory array. This component contains the verified RTL Verilog code of the memory structure and round robin arbiter and implements a queuing system based on dynamically allocated memory per queue.

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