• Deficit round robin multi-FIFO queuing

    This design is a queuing system based on FIFOs and deficit round robin arbitration (DRR). The typical usage of this queuing structure is to store data from multiple sources, select one of them according to the deficit fair arbitration method and drive it to a shared resource such as a communication link or processing unit.

  • Slow signals synchronizer

    Slow signal synchronizer offers a solution for transferring relatively slow and static vectors across clock domains without risking meta-stability and coherency problems resulting from partial vector synchronization. The synchronizer is most suitable for configuration and status synchronization.

  • barrel shifter

    A Barrel Shifter is a logic component that perform shift or rotate operations. Barrel shifters are applicable for digital signal processors and processors. This component design is for a natural size (4,8,16…) barrel shifters that perform shift right logical, rotate right, shift left logical, and rotate left operations depending on the instantiation parameters.

  • PPC based deficit work conserving round robin arbiter

    The deficit round robin arbiter (DWCRRB or DRR) is a variation of the round robin arbitration where the arbitration decision is focused on the processing length of the currently selected element when using the downstream shared resource.

  • Dynamic strict priority arbiter

    The dynamic priority arbiter enables the priorities of the requestors to be changed during arbiter operation, allowing different parameters such as congestions, waiting time, data size etc… to affect the requestor’s priority.

  • Work Conserving Round Robin Arbiter

    Round robin arbitration is a scheduling scheme which gives to each requestor its share of using a common resource for a limited time or data elements. The basic algorithm indicates that once a requestor has been serves he would “go around” to the end of the line and be the last to be served again. Using a parallel prefix computation (PPC) speeds up the next granted requestor calculation and improves the circuit timing. This Component contains the verified verilog RTL code for a work conserving round robin arbiter, meaning there are no cycles spent on requestors that are inactive.

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