Arbiter collection

 
 
Verified

Arbiters are design elements targeted for resolving access to shared resources by multiple requestors. The arbitration scheme is typically based on a specific fairness algorithm, allocating each requestor its share of the resource. Arbiters are commonly used in queueing structures of communications and computing designs. This component collection contains some of the most widely used arbiters including several versions of round robin arbiter as well as a dynamic priority arbiter. The components contained in this collection are:

1.    Round robin arbiter

2.    Weighted Round robin arbiter

3.    Deficit Round robin arbiter

4.    Dynamic priority arbiter

Product Deliverables

  • verified RTL code
  • Detailed design documentation
  • 1 year support

 

Round robin arbiter

Round robin arbitration is a scheduling scheme which gives to each requestor its share of using a common resource for a limited time or data elements. The basic algorithm indicates that once a requestor has been serves he would “go around” to the end of the line and be the last to be served again. Using a parallel prefix computation (PPC) speeds up the next granted requestor calculation and improves the circuit timing. This Component contains the verified verilog RTL code for a work conserving round robin arbiter, meaning there are no cycles spent on requestors that are inactive.

Block diagram

The below block diagram shows the basic PPC based work conserving round robin arbiter and the pipeline version.

round robin arbiter block diagram

features

  • Work conserving round robin arbitration with equal share of the number of grants per all requestors
  • No time slots wasted on inactive requestors
  •  ack signal, for downstream stall of the arbiter, the grant vector will change only if ack is asserted. For a new grant every cycle; the ack signal can be kept asserted.
  • Fast parallel computation using Parallel prefix computation.
  • Valid output indicating the arbiter grant is valid.
  • Wrap around functionality, when the round robin reaches the last requestor, it will return to the requestors at the beginning without losing cycles.
  • Parameterized number of requestors, enabling flexibility in using the arbiter in different applications.
  •  Parameterized output stage, providing either one-hot, binary decoded or thermometer decoded output for usage in different applications.

Optional features

Optional features are available through different downloadable files

  • Pipeline integration support.
  • synchronous and asynchronous reset.

Weighted round robin arbiter

The weight round robin arbitration functionality allows each requestor to be granted a number of acknowledges according to its predefined weight, so using this arbiter results in a balanced number of acknowledges for each valid requestor.Using a parallel prefix computation (PPC) speeds up the next granted requestor calculation and improves the circuit timing.

This Component contains the verified verilog RTL code for a work conserving round robin arbiter, meaning there are no cycles spent on requestors that are inactive.

Block diagram

The below basic block diagram shows the weighted PPC based work conserving round robin arbiter.

weighted round robin arbiter block diagram

Features

  • Work conserving round robin arbitration with weighted share of the number of grants per each requestor setting strict ratio of grants between all constantly active requests.
  • Weight setting for each of the requestors. A weight of 0 indicates that the requestor is masked, so its request will be ignored.
  • No time slots wasted on inactive requestors.
  • ack signal, for downstream stall of the arbiter, the grant vector will change only if ack is asserted. For a new grant every cycle; the ack signal can be kept asserted.
  • Fast parallel computation using PPC method.
  •  Valid output indicating the arbiter grant is valid, meaning there are valid requests asserted.
  • Wrap around, meaning that the round robin reaches the end of the vector, it will return to the requestors at the beginning without losing cycles.
  • Parameterized output stage, providing either one-hot, binary decoded or thermometer decoded output for usage in different applications.

Optional features

  •  Optional features are available through different downloadable files
  •  synchronous and asynchronous reset.

Deficit Round Robin Arbiter

The deficit round robin arbiter (DWCRRB or DRR) is a variation of the round robin arbitration where the arbitration decision is focused on the processing length of the currently selected element when using the downstream shared resource. The arbiter balances the overall processing time assigned to each requestor by looking at processing length information from the selected element during arbitration. Round robin arbitration is a scheduling scheme which gives to each requestor its share of using a common resource for a limited time or data elements. The basic algorithm indicates that once a requestor has been serves he would “go around” to the end of the line and be the last to be served again. The typical case for using a deficit work conserving round robin arbiter is for fairly selecting data packets to be sent on a communication link. This component contains the verified RTL Verilog code of a deficit work conserving round robin arbiter.

Block diagram

The below basic block diagram shows the deficit PPC based work conserving round robin arbiter.

 

deficit work conserving round robin arbiter

Features

  • Work conserving round robin with deficit arbitration methods.
  • Datasize input for each of the requestors. Indicating the data size of the next element from the requestor.
  • Constant input quantum value.
  •  No time slots wasted on inactive requestors.
  •  ack signal, for downstream stall of the arbiter, the grant vector will change only if ack is asserted. For a new grant every cycle; the ack signal can be kept asserted.
  • Fast parallel computation using PPC method.
  • Valid output indicating the arbiter grant is valid, meaning there are valid requests asserted.
  • Wrap around, meaning that the round robin reaches the end of the vector, it will return to the requestors at the beginning without losing cycles.
  • Parameterized output stage, providing either one-hot, binary decoded or thermometer decoded output for usage in different applications.

Optional features

Optional features are available through different downloadable files

  • synchronous and asynchronous reset.

Dynamic priority arbiter

The dynamic priority arbiter enables the priorities of the requestors to be changed during arbiter operation, allowing different parameters such as congestions, waiting time, data size etc… to affect the requestor’s priority. The arbitration between requestors of equal priority is using either a strict priority based on requestor ID or round robin arbitration.

The arbiter implements a two-step arbitration process. The first is a fixed priority arbitration based on the valid priorities of the requestors. Once the highest priority with available requestors is selected, the second stage of arbitration selects between those requestors of the same priority by strict priority using their requestor ID or by round robin.

Block diagram

The below basic block diagram shows the dynamic priority arbiter.

dynamic priority arbiter

Features

  • Dynamically changeable priority per requestor.
  • Strict priority according to request ID or round robin among equal priority requests.

Optional features

Optional features available through different file download

  • synchronous and asynchronous reset.
  • Type of second stage arbitration, either strict priority or round robin.

Round Robin Arbiter

The Work conserving round robin arbiter is designed to be used in the context of pipelined decision blocks and within multiple queue or FIFO systems where its advantages are:

  1. Enable fair arbitration, granting all requestors the same number of times.
  2. The pipelined version can be easily integrated into flow controlled, pipeline decision blocks.
  3. Simple integration into FIFO systems. See application note below.
  4. Fast PPC selection logic

Care must be taken in the following issues:

1.    When the request vector is fast changing and has bits that get de-asserted, overall fairness may be compromised.

Integrating with a FIFO system

The typical usage of a round robin arbiter for a FIFO system with multiple FIFOs and an arbiter to select which of them will be extracted is implemented through the following connections:

  1.  Connect the request vector to the ~empty or each of the FIFOs so when the FIFO is not empty, a request to the arbiter will be asserted.
  2.  Connect a one-hot grant vector (OUTPUT_TYPE=1) to the extract of the FIFOs. This would be masked with the downstream flow control signaling.
  3. Connect the arbiter ack signal to the downstream flow control signal so each time there is no flow control, the ack would be asserted providing that the arbiter valid is asserted.

More details can be found in the queuing component type where such a components can be found.

Weighted round robin arbiter

The weighted work conserving round robin arbiter is designed to be used in the context of pipelined decision blocks and within multiple queue or FIFO systems where its advantages are:

  1. Enable fair arbitration, granting all requestors the number of times corresponding to their weight.
  2. Simple integration into FIFO systems.
  3. Fast PPC selection logic

Care must be taken in the following issues:

  1. When the request vector is fast changing and has bits that get de-asserted, overall fairness may be compromised.

Integrating with a FIFO system

The typical usage of a round robin arbiter for a FIFO system with multiple FIFOs and an arbiter to select which of them will be extracted is implemented through the following connections:

  1. Connect the request vector to the ~empty or each of the FIFOs so when the FIFO is not empty, a request to the arbiter will be asserted.
  2. Connect the weight vector to external configuration registers, setting the priority for each queue.
  3. Connect a one-hot grant vector (OUTPUT_TYPE=1) to the extract of the FIFOs. This would be masked with the downstream flow control signaling.
  4. Connect the arbiter ack signal to the downstream flow control signal so each time there is no flow control, the ack would be asserted providing that the arbiter valid is asserted.

Deficit Round Robin Arbiter

The typical case for using a deficit work conserving round robin arbiter is for arbitrating data packets to be sent on a communication link. In this case, the arbitration would prevent requestors with large packets from dominating the link and give a fair share of the link bandwidth to requestors with shorter packet sizes.

The arbiter can be integrated with a multiple FIFO or multiple queue architecture or into a pipeline.

Integrating with a FIFO system

The typical usage of a round robin arbiter for a FIFO system with multiple FIFOs and an arbiter to select which of them will be extracted is implemented through the following connections:

  1. Connect the request vector to the ~empty or each of the FIFOs so when the FIFO is not empty, a request to the arbiter will be asserted.
  2. Connect the datasize vector to the FIFO output data size portion.
  3. Connect a one-hot grant vector (OUTPUT_TYPE=1) to the extract of the FIFOs. This would be masked with the downstream flow control signaling.
  4. Connect the arbiter ack signal to the downstream flow control signal so each time there is no flow control, the ack would be asserted providing that the arbiter valid is asserted.

Dynamic priority arbiter

Integrating with a FIFO system

The typical usage of a dynamic priority arbiter for a FIFO system with multiple FIFOs and an arbiter to select which of them will be extracted is implemented through the following connections:

  1. Connect the request vector to the ~empty or each of the FIFOs so when the FIFO is not empty, a request to the arbiter will be asserted.
  2. Connect a one-hot grant vector (OUTPUT_TYPE=1) to the extract of the FIFOs. This would be masked with the downstream flow control signaling.
  3. Connect the arbiter ack signal to the downstream flow control signal so each time there is no flow control, the ack would be asserted providing that the arbiter valid is asserted.