Arbiters

  • arbiter collection

    Arbiters are design elements targeted for resolving access to shared resources by multiple requestors. The arbitration scheme is typically based on a specific fairness algorithm, allocating each requestor its share of the resource. Arbiters are commonly used in queueing structures of communications and computing designs.

  • PPC based weighted work conserving round robin arbiter

    The weight functionality of the round robin arbiter allows each requestor to be granted a number of acknowledges according to its predefined weight, so using this arbiter results in a balanced number of acknowledges for each valid requestor.Round robin arbitration is a scheduling scheme which gives to each requestor its share of using a common resource for a limited time or data elements. The basic algorithm indicates that once a requestor has been serves he would “go around” to the end of the line and be the last to be served again. Using a parallel prefix computation (PPC) speeds up the next granted requestor calculation and improves the circuit timing.

  • PPC based deficit work conserving round robin arbiter

    The deficit round robin arbiter (DWCRRB or DRR) is a variation of the round robin arbitration where the arbitration decision is focused on the processing length of the currently selected element when using the downstream shared resource.

  • Dynamic strict priority arbiter

    The dynamic priority arbiter enables the priorities of the requestors to be changed during arbiter operation, allowing different parameters such as congestions, waiting time, data size etc… to affect the requestor’s priority.

  • Work Conserving Round Robin Arbiter

    Round robin arbitration is a scheduling scheme which gives to each requestor its share of using a common resource for a limited time or data elements. The basic algorithm indicates that once a requestor has been serves he would “go around” to the end of the line and be the last to be served again. Using a parallel prefix computation (PPC) speeds up the next granted requestor calculation and improves the circuit timing. This Component contains the verified verilog RTL code for a work conserving round robin arbiter, meaning there are no cycles spent on requestors that are inactive.