Asynchronous fifo synchronizer

 
SiliconProven

Asynchronous FIFO synchronizer offers a solution for transferring signals and vectors across clock domains without risking meta-stability and coherency problems resulting from partial vector synchronization. The synchronizer is suitable for synchronization of data and control information between asynchronous domain of known data and clock ratio. This component contains a verified Verilog RTL code of the asynchronous FIFO synchronizer with parametric data bus width. The synchronizer allows the transfer of wide vectors across clock domain with minimal timing requirements and no meta-stability issues. The synchronizer uses a FIFO with one clock domain for load and another clock domain for extract. Data is written into the FIFO at one clock domain, and only later is read from the FIFO in the other clock domain. The FIFO itself can be implemented using an embedded memory or an array of registers.

There are several types of asynchronous FIFOs, suited for different applications. This component implement a generic dual clock FIFO meaning that it has all the functionality of a FIFO like empty and full indications and ability to flow control the FIFO. The FIFO depth is a natural power of 2 with a minimal depth of 16 entries (actually 10 is enough), to accommodate the round trip required for full flow control without bubbles. Other applications may not require flow control, so data is extracted from the FIFO whenever it is available, so a depth of 8 may be sufficient.

Block diagram

Asynchronous FIFO block diagram

 

Features

  • Full synchronization, independent of clock frequencies.
  • Grey code FIFO pointer synchronization.
  • Parameterized Natural depth, of 16, 32, 64 etc...
  • Almost full indication with parameter selectable depth for flow control

Optional features

Optional features are available as different downloadable files

  • Memory array implemented using dual clock RAM embedded memory.
  • Synchronous and asynchronous reset.

Deliverables

  • verified RTL code
  • Access to detailed design documentation
  • 1 year support and customization service.

parameters table

Parameter

Valid values

description

WIDTH

Any

FIFO width

DEPTH

16,32,64…

FIFO depth, required depth > 10 for flow control

ALMOSTFULL_DEPTH

up to the FIFO DEPTH -10

the almost full depth is the number of available entries in the FIFO when the almostfull flow control signal is asserted. a value of 3 for example, means that there are 3 available entries before the FIFO gets full. The almostfull depth should always enable 10 entries. So for a 16 entries FIFO, the maximal almostfull depth is 6.

Interface table

Signal name

Direction/width

description

wclk

Input

Clock signal for write clock domain, free running clock, needs to toggle for proper functionality.

Resetb

Input

Active low reset.

rclk

input

Clock signal read clock domain.

Load

Input

Indicating a data is to be loaded into the FIFO. When the FIFO is full, the load signal is ignored.

Extract

Input

Indicating that data is to be extracted from the FIFO. When FIFO is empty, the extract signal is ignored.

Datain

Input [WIDTH-1:0]

Data input vector.

Dataout

Output [WIDTH-1:0]

Data output vector.

Empty

Output

FIFO empty indication to the read side.

Full

Output

FIFO full indication to the write side.

almostfull

Output

FIFO almostfull indication

Functionality

The functionality of the asynchronous FIFO is very similar to that of a basic FIFO. When the load signal is asserted and full indication is not set, the data on the datain bus will be written into the memory array. When the full indication is set, the upstream logic is expected to stall further loads into the FIFO. In case the load signal is asserted when the FIFO is full, the load would be ignored and the data would be dropped.

The extract operation can be performed when the FIFO is not empty, so when the empty indication is set, the extract operation is ignored.

Synchronization of write pointer

The synchronizer uses Grey code to prevent meta stability between the two clock domains. The pointer on the write side is encoded from binary to Grey code and that goes through a full synchronizer, and then translated again into binary on the read side. The synchronized write pointer is than compared to the read pointer to generate the empty signal used for flow controlling the FIFO extract side. As the comparison between the changed write pointer and the read pointer is inevitably later than the actual load of data to the memory array, the FIFO depth should be able to absorb further loads happening during that delay time. For more details about the Grey code and its advantages for clock domain crossing refer to the decoders section here.

Synchronization of read pointer

The read pointer synchronization uses a Grey code encoding to overcome the uncertainties of clock domain crossing and prevent unexpected read pointer values at the write clock domain. The read pointer is encoded into Grey code, goes through a full synchronizer and then decoded back into binary, to be compared with the write pointer to generate the full indication. the full indication is used for flow control of the loaded data. The comparison is late, compared to the actual read operation, so more entries may be extracted during that time. The FIFO depth needs to accommodate this delay in order to prevent unnecessary bubbles on the read side.

FIFO depth consideration

The FIFO depth needs to accommodate the following considerations:

  1. Round trip delay worst case occurs when the FIFO is full and flow controlled by downstream logic, and the, flow control is removed and a burst of consecutive extract operations is performed. Further load operations are blocked until the full signal is negated. After the full is negated, it will take the synchronization delay for the write pointer to be changed at the read side. In order for the FIFO not to become empty and insert bubbles on the extract path, the empty signal should not be set before the write pointer for the first write goes through the synchronizer. The depth of the FIFO is therefore required to be at least 10 cycles, 5 in each direction for updating the pointer and for the worst case synchronizer delay of 4 cycles.

  2. The usage of the FIFO synchronizer assumes that the data rate of the read side is at least as fast as the write side, so the FIFO does not get overflowed and generate unnecessary flow control. The depth of the FIFO should assume temporal differences in the data rate and accommodate some extra entries for the purpose of buffering such effects. The best practice for eliminating the risks of unnecessary FIFO full indication is the allow for some speed-up of the read side over the write side of the FIFO.

In order to accommodate both requirements, the FIFO depth recommended for a full flow controlled implementation is 16 cycles. The behavior of the FIFO should be checked in the actual environment, assuming that in steady state where data rate is equal, the FIFO should not reach full or empty. When using simple simulations, the actual FIFO level should be 1-2 entries from full or empty cases. For a single direction flow control, where the extract signal is constantly asserted, a depth of 8 should be sufficient and the FIFO should not reach a status of full.

almost full FIFO functionality

The FIFO would assert the almostfull signal some cycles before the FIFO gets full, this will allow the flow to be stopped further up the pipe.

The FIFO would absorb the entries which are in flight so no data is lost. the ALMOSTFULL_DEPTH parameter should be set according to the number of sampling pipe stages before the FIFO.

The disadvantage of the almostfull comes where the FIFO is read, the flow control would be de-asserted only after there are ALMOSTFULL_DEPTH free entries in the FIFO. to prevent bubbles at the FIFO output and FIFO underruns, the FIFO depth should be at least double the size of the ALMOSTFULL_DEPTH so the it does not get empty before the new entries are loaded once the almostfull signal is de-asserted.

Reset

The reset signal is assumed to be capable of resetting both clock domains. When using synchronous reset, both clocks must be toggling when reset is de-asserted.

Test Items

the below table summarizes the test items that were checked for this component

Item name

Description

Clock frequencies

Check synchronizer for different clock frequencies, keeping data ratio equal, expected not to overflow or under-run.

Clock alignment

Check different clock alignments to find the worst case logic delay.

Worst case round trip

As described above the worst case round trip is when the FIFO is stalled by downstream logic and is full, and then the stall is released, the FIFO is not to get empty and cause bubbles. Check for safety 2 entries at least in this case.

Data ratios

Check different data rations for load and extract, see that the FIFO hold when empty and when full.