Basic fifo

 
 
Verified

FIFO is an acronym for First In, First Out data organization method. FIFOs are widely used in logic design for buffering, queuing and management of rate, priorities and flow control in data applications. A FIFO consists of a read pointer and a write pointer, pointing to entries in a storage array typically, made of flip-flops.

This component contains the verilog code for the basic 2n deep FIFO implementation where the available depths are 4,8,16,32,64....256... The implementation includes flow control indications for FIFO full, FIFO empty.A flop-based FIFO can be integrated into a pipeline structure as it serves as a single sampling stage when empty, and can generate pipe stall  for upstream logic when full.

block diagram

 

Basic FIFO block diagram

Features

  • Single clock synchronous functionality
  • Asynchronous reset of FIFO pointers
  • Flip-flop based memory array
  •  
  • Parameter controlled depth
  • Parameter controlled width
  • Empty and full indications
  • Prevents load when FIFO is full
  • Prevents extract when FIFO is empty
  • parametrized Depth which are powers of 2 like 2, 4, 8, 16, 32,  … , 128,…

Deliverables

  • verified RTL code
  • Access to detailed design documentation
  • 1 year support and customization service.

 

Parameters table

Parameter

Valid values

description

WIDTH

Any

FIFO width

DEPTH

2, 4, 8, 16, 32,…

FIFO depth

interface table

Signal name

Direction/width

description

clk

Input

Clock signal

resetb

Input

Active low reset signal, when asserted, pointers would return to zero and empty indication would be set

load

Input

Indicates the FIFO is to be written, will be ignored when FIFO is full and extract is de-asserted

extract

Input

Indicates a FIFO entry is to be read, will be ignored when FIFO is empty

empty

Output

Indication that the FIFO is empty. Extract operations are ignored while FIFO is empty

full

Output

Indication that the FIFO is full. Load operations are ignored while FIFO is full

datain

Input [WIDTH – 1:0]

Data input

dataout

Output [WIDTH – 1:0]

Data output

 

FIFO functionality

The generic synchronous FIFO for log2 depths is designed with a flip-flop memory array and a set of read pointer and write pointer.

The FIFO reset functionality is either synchronous or asynchronous and should be used according to the overall reset policy of the instantiating device.

The status indications are implemented using a wrap-around bit in the pointers.

When the FIFO is full, simultaneous load and extract is supported, but care must be taken as the upstream logic has no indication whether the data has been loaded or dropped without evaluating the extract signal. For that reason, the typical application would mask the load signal with the full indication, preventing the simultaneous load and extract while the FIFO is full. 

The FIFO depth and width are parameters that can be set to any valid value at instantiation. Additional parameter sets the width of the required address of the FIFO i.e., for a FIFO of depth 16, 4 bits would be required.

Basic flop based FIFO should be used only for relatively small arrays where timing requirement can be met, for bigger arrays, a memory based FIFO should be used.

Load and extract

The load and extract operations of the FIFO impact the FIFO pointers. When the load signal is asserted, the data on the datain is loaded into the position pointed by the write pointer and the pointer is then incremented by 1 to point to the next FIFO entry. If the FIFO full indication is asserted, and the extract signal is not asserted, the load operation would be ignored and the pointer would not be incremented.

Simultaneous load and extract operations to the FIFO when full indication is asserted will result is a write of the datain to the FIFO and a read to the dataout. The full indication will remain asserted in that case.

The below diagram shows the load and extract operations and the impact of them on the full and empty signals

FIFO load extract waveform

In the above drawing, at time T1, the empty signal is de-asserted after the first write operation is complete. At T2, simultaneous load and extract operations are performed when the FIFO is full. The result is that the FIFO remains full as data D5 is written into the FIFO and D1 is read, at the same time. At time T3, the last written entry is extracted from the FIFO and the empty signal is asserted.

Reset

The fifo_basic_asyncrst uses asynchronous active low reset signal. Once asserted, the pointers would return to their default value of 0 and the FIFO empty signal would be asserted.

The fifo_basic_syncrst uses synchronous active low reset signal. Once asserted, the pointers would return to their default value of 0 at the rising edge of the clock and the FIFO empty signal would be asserted.

The reset operation has no impact on the content of the memory array itself.

Test Items

The below table summarizes the test items that were checked for the basic FIFO

some of the items are relevant only for specific examples.

Item name

Description

Reset functionality

Check reset assertion during operation, see that the pointers return to zero.

empty

Write to FIFO, check that FIFO empty indication is de-asserted.

Full functionality

Write to the FIFO the same number of entries as its depth, check that the full indication is asserted

Load when full

Load the FIFO when full indication is asserted, check that the loaded data is ignored and the FIFO ignores the load.

Simultaneous load and extract when full

Perform a simultaneous load and extract operations while the FIFO is full, see that both operations work, continue for multiple times, until written entry is read out.

   

 

application note

Basic flop based FIFO should be used only for relatively small arrays where timing requirement can be met, for bigger arrays, a memory based FIFO should be used.

The integration of the FIFO into a pipeline design requires the attention to flow control indications. The FIFO empty signal should be used for signaling downstream logic the there is available data at the FIFO outout. the full indication should be used for signaling the upstream logic to stall the pipe so data is not lost.

Timing considerations

Data  in

When looking at the timing considerations for datain signal, one should look into the fanout of each data bit. The data bits actually reach each and every entry of the FIFO. A timing issue may arise for FIFOs with high entry count.

Data out

The timing for datout in the typical FIFO results from the number of entries as well. For each data bit, an output multiplexer with the number of entries is created. The number of logical stages of the output select depends on the number of entries.