Chip clock and reset initialization reference design


Every ASIC device requires a power-up and initialization sequence, enabling clock to start and reset to be propagated through to all parts of the logic. The clocking and reset initialization sequence is different from other purely logical parts as it handles slow signals external to the device, an analog PLL and depends on the sequencing of the device power rails, external clock generators and I/O pads. In many cases, testability and backup logic is also included, further complicating this delicate logic. This component is a simplified example of a device clocking and reset sequence and can be used as a reference and starting point for the implementation of this logic. This component contains RTL Verilog code for a reference design for a chip level clock and reset synchronization and initialization. The component contains the PLL startup logic, reset synchronization and propagation and handles clock selection and bypassing as well as reset distribution at the chip top level.

this component is a reference design for RTLery device clocking and reset servide

Block Diagram

clock and reset initialization block diagram


  • External reset signal synchronization and hazard filtering logic.
  • PLL instantiation, including reset and lock handling.
  • PLL configuration sampling from external pads.
  • PLL bypassing control and clock multiplexing.
  • Core reset signal generation and propagation for safe reset distribution.
  • Core clock multiplexing, for clock bypass mode.

note:  the clock divider is not included in this core

Product Deliverables

  • Verified RTL code of the reference design 
  • optional service for specific PLL models according to PLL specifications
  • optional service for customization for reset sequence requirements
  • optional service for customization for clock distribution requirements
  • Access to detailed design documentation

Parameters Table


Valid values




The number of reference clocks required for PLL lock as measured from the de-assertion of the PLL reset.



The number of reference clocks required for the PLL to reset.



The width of the counters used for the highest number of delay cycles from the lock and reset delay parameters.



Width of a counter that represents the highest ratio between the slow reference clock and the PLL clock.



Size of the PLL configuration vector.



Number of flops to use for reset synchronization. See more details under implementation tab.



Number of flops to use for reset filtering. See more details under implementation tab.

Interface Table

Signal name





Reference clock, typically would be the output of a clock pad or the PLL itself.



PLL bypass indication, from external pad.



PLL configuration vector input from external pads typically would contain the pre-divider and post divider ratios and some analog settings.



Main device reset, coming from external pad.



Test mode, used for selecting the reference clock at the clock multiplexer for testing purpose.



Core clock, output to rest of the device.



Core reset, output to the rest of the device.


The functionality of this logic is to streamline the initialization sequence of the clocking and reset of an ASIC device by controlling the order of events that lead to robust PLL initialization and resetting of all the blocks in the device. As the implementation of such logic is dependent on the specific PLL, clocking requirements, testability requirements, system integration issues and more, this design addresses the most common use case and can be used as a reference for designing for the full set of requirements.

External Reset Synchronization

The external reset going into the device requires special attention because of its importance to the device functionality. The reset signals need to affect the logic inside the device, very early in the initialization process, so the logic can be put into a known state as fast as possible, preventing unexpected behavior. The external reset signal may also be a slow to change signal, and may create false transitions on the internal reset signals.

A synchronizer on the reset signal can prevent it from getting into meta-stability during power-up, allowing more time for stabilization and a simple filter can ensure, the internal logic only recognizes the reset as de-asserted after it is stable for a few cycles. On the other hand, the assertion of reset needs to affect the internal logic independently of the device clocks, so the leading edge of the external reset is to be propagated asynchronously to the rest of the device.

PLL Initialization

The initialization of the device PLL is an essential part of the device bring-up process. Sequencing the PLL startup with the reset propagation, ensures that the logical blocks receive only valid and stable clocking and reset.

There is a large variety of PLLs available, but the main requirements of the initialization sequence are the setting of the PLL divide ratios, reset of the PLL logic for a minimal time period, and a lock time, allowing the PLL to lock on to the reference signal and get to the required frequency before its output is safe to use.

Reset Distribution

The distribution of reset to the logical blocks of the device may be done either synchronously or asynchronously on the device top level. In the context of the blocks, reset de-assertion is typically synchronous, allowing for the block design to be clearly defined for timing closure of removal and recovery flip-flop timing requirements. In some cases, the top level reset propagation would also be synchronous, ensuring reset de-assertion time is well defined for all flops of the device. For all distribution options, the reset assertion is typically required to be independent of clocking and therefore asynchronous.

Clock Multiplexing

For different purposes, such as backup and test modes, most devices require the option to drive an externally generated clock on the clock network. This clock would typically be the reference clock used for the PLL, but can also use a separate dedicated bypass clock signal.

For devices using synchronous reset, there is a need to drive a clock through the clock network so the reset would be propagated to all the logic and put the device into a known state.

For all purposes, it is a good practice, to drive a clock into the device, as soon as possible and later switch to the PLL clock when it is locked and ready.

Initialization Sequence

The initialization sequence contains the following steps:

  1. External reset signal synchronization and filtering.
  2. PLL configuration sampling from bond options or dedicated pads.
  3. PLL reset assertion for the required time period.
  4.  PLL reset de-assertion and PLL locking
  5. Clock switching, enabling the core logic to receive the PLL clock.
  6. Core reset de-assertion.

A sequence for core reset de-assertion using PLL bypass mode is also implemented.

Test Items

the below table summarizes the test items that were checked

Item name


PLL initialization sequence

Run the full sequence using PLL output

Bypass initialization sequence

Run the full sequence using bypass clock

Clock switch

Clock switching back to bypass clock after initialization



electing Correct Parameters

Setting the correct parameters for the module is essential, below listing issues to consider when setting the parameters:




The number of reference clocks required for PLL lock as measured from the de-assertion of the PLL reset. This is a function of the PLL specification for the lock time and the frequency of the reference clock at its highest configuration. For safe results, some additional time should be taken.


The number of reference clocks required for the PLL to reset. This parameter is a function of the PLL specification for minimal reset time and the highest reference clock frequency.


The width of the counters used for the highest number of delay cycles. Typically this would be the PLL lock time, but care must be taken, to allow long enough delay.


Width of a counter that represents the highest ratio between the slowest reference clock and the fastest PLL clock. This parameter is used by the glitch free mux.