On-chip frequency measurement counter

 
SiliconProven

The frequency counter can be used for measuring clock rates, of external or internally generated clocks for the many purposes, such as configuration, validation tasks and more. The measured clock is treated as asynchronous to the control clock and any clock frequency relation can be measured. This component contains RTL Verilog code for a frequency counter designed to measure the frequency of a clock.

The implementation of the frequency counter is based on a time counter running in the control clock and a second counter running at the measured clock. The period of the time counter is typically set to 1 second so the number of clock cycles counted in the measurement counter during this period is actually the frequency of the measured clock.

Block diagram

frequency measurement block diagram

 

Features

  • Clock rate counting, for measuring the frequency of a clock.
  • Parameterized time counter width.
  • Parameterized frequency counter width.
  • Overflow indication.
  • Time counter period signal, enabling configuration for different frequencies.

Product deliverables

  • Verified RTL code and simulation test-bench
  • Access to detailed design documentation
  • One year support and customization service.

parameters table

Parameter

Valid values

description

WIDTH

Any

Width of the frequency counter.

TIMEWIDTH

Any

Width of the time counter.

Interface table

Signal name

Direction/width

description

Msrclk

Input

Measured clock

ctrlclk

Input

Clock signal

Resetb

Input

Reset signal

freq_counter_period

Input [TIMEWIDTH-1:0]

Constant or configuration register value indicating the number of clocks for a predefined time period (typically one second)

freq_time_enable

Input

Enable counters.

freq_cntr_val

Output [WIDTH-1:0]

Frequency counter result, updated each time the time counter expires.

freq_cntr_overflow

Output

Overflow indication, when this bit is set, the frequency counter value is not valid.

Functionality

The Frequency counter allows the measurement of the rate of a secondary clock in the design for debug, validation and optimization purposes. The Frequency counter has two counters, one for measuring a predefined time period using the main control clock, and the other for measuring the number of clocks occurring during that time, running in the measured clock. In case the time counter, counts a period of 1 second, the resulting frequency counter, is actually the rate of measured clock.

Overflow case

The overflow signal serves as an indication that the frequency counter has overrun. Typically, in order to reduce the amount of logic used for the frequency counter, the number of bits used is low, accommodating the expected number of clocks during the time period. For example, for measuring a slow clock, the expected result is low, so a smaller counter is enough and in case the clock is faster, an overflow indication would be sufficient to signal that the frequency cannot be measured for this time period.

Reset

The design can be reset either synchronously or asynchronously, depending on the overall reset policy of the instantiating design.

Test Items

the below table summarizes the test items that were checked

Item name

Description

Frequency rate

Measure with different rates of clocks. Use, jittering clock frequency to induce multiple different measurements.

Counter size

Change event counter size to produce overflow.

Overflow

Check overflow event is set only for the correct cases.

 

Selecting width parameters

Setting the correct width for the counters is essential for proper operation. The time counter should be able to accommodate a 1 second delay, so for example, at 250Mhz, the counter should be set to 1,000,000,000/4 = ‘hEE6B280 so for this frequency of control clock you would need 28 bits at least. Note that measuring with higher number of bits may be more accurate and result in fewer variations between consecutive measurements.

For the frequency counter to function properly and enable measurement of the intended clock frequency, care should be taken for the following cases:

                         Case

Requirement

Measured frequency higher than control frequency

Set the WIDTH parameter to be higher that the TIMEWIDTH, allowing for the maximal frequency ratio.

Measured frequency lower than control frequency

Set the WIDTH parameter to be lower that the TIMEWIDTH, allowing for the maximal frequency ratio.