Clocking&reset

  • clock Deskew DLL

    The RTLery Deskew DLL core implement a fully digital delay-line based DLL structure that effectively eliminates the skew between two identical frequency clock signals. The Delay-Locked Loop (DLL) provides an on-chip digital deskew circuit that effectively generates clock output signals with a net zero delay between them. The DLL can be used for eliminating the delay of a clock insertion delay effectively eliminating delay from the external clock input pin to the clock tree loads within the device.

  • Chip clock and reset initialization reference design

    Every ASIC device requires a power-up and initialization sequence, enabling clock to start and reset to be propagated through to all parts of the logic.

  • Clock frequency divider

    Clock frequency dividers generate slower clocks from a faster reference. Typically additional clock division is required for applications requiring very slow clocks, such as video and voice processing devices or the case where fine granularity of division is required. Such a clock divider would typically be placed after the device PLL.

  • glitch free clock multiplexer(mux)

    A clock glitch-free clock multiplexer serves to switch between two asynchronous clocks while protecting downstream logic from clock glitches. The de-glitch clock mux also enables switching when one or both of the clocks are not toggling. This component contains the verified RTL code of the clock switch as well as documentation and timing and physical design instruction.

  • Counter clock divider

    Clock dividers generate slower clocks from a faster reference clock. The simplest clock divider divides a clock frequency by 2 using a single flop and an inverter.  Using the same concept, a counter based clock divider can divide a clock by 2, 4, 8, etc. This component contains RTL Verilog code for clock dividers based on counters.

  • on-chip frequency measurement counter

    The frequency counter can be used for measuring clock rates, of external or internally generated clocks for the many purposes, such as configuration, validation tasks and more. The measured clock is treated as asynchronous to the control clock and any clock frequency relation can be measured.

  • Ring oscillator performance monitor

    This component contains verified RTL Verilog code for a process monitor counter designed to measure the frequency of a ring oscillator output for the purpose of correlating process voltage and temperature between devices and measuring on-chip variation (OCV). A ring oscillator is a device composed of an odd number of logical inverters whose output oscillates between the two logical levels.