• Interconnect Interface FIFO

    An interface FIFO serves to facilitate chip level integration by providing a full handshake interface between two block that is sampled in both directions. sampling signals in both sending and receiving blocks is a way of reducing the complexity of chip level timing closure.

  • Daisy Chain Control and status bus

    The Control and Status Registers daisy chain connectivity module is to connect a central logic (CPU, DMA controller) to multiple different blocks on a chip using daisy chained bus. The main advantages of daisy chain connectivity are the flexibility of adding new slaves (targets) and the low number of signals running long distance from the central logic to each of the target.