Counter clock divider


Clock dividers generate slower clocks from a faster reference clock. The simplest clock divider divides a clock frequency by 2 using a single flop and an inverter.  Using the same concept, a counter based clock divider can divide a clock by 2, 4, 8, etc. This component contains RTL Verilog code for clock dividers based on counters. The dividers are used for generating lower frequency clocks from a faster reference clock.

Block diagram

counter natural clock divider block diagram


  • Divides with all natural power of 2 ratios up to the MAXRATIO
  • 50% duty cycle output clock
  • Glitch free clock ratio change
  • Can be connected to a constant divratio if necessary.
  • Separate controlclk for sampling the divratio information, provides flexibility in clock scheme and timing closure.
  • Synchronization of divratio, so Controlclk can be asynchronous to refclk
  • Single divclk output that can serve as the clock source for block logic.
  • Asynchronous active low reset, care must be taken for proper reset separation and ordering when using this divider in a synchronous reset block.

Optional Features

Optional features are available through different downloadable files

  • Synchronous and asynchronous reset


  • verified RTL code
  •  Access to detailed design documentation
  • 1 year support and customization service.

parameters table


Valid values




Maximal clock division ratio, controls the width of the division counter.

Interface table

Signal name





Reference clock to be divided



Divided clock



Control clock, used for sampling control information. Can be connected to the balanced version of the divclk if necessary.



Asynchronous active low reset, used for resetting the control logic



Used for resetting the divide counter



Log(2) of MAXRATIO rounded up +1

Divide ratio, possible values are 2, 4, 8, 16 …MAXRATIO


Synchronization logic

The clock divider contains synchronization logic for the divratio input, thus separating the domain of the clock divider itself from the control logic, resolving internally the asynchronous relation between the control clock and the reference clock. This synchronization is required as the refclk domain of the divider is not balanced to the rest of the block while the control clock can be a balanced clock, simplifying the timing of the divratio signal.

The control clock can be a product of the divider output. Since the divider starts producing a clock  when its reset signal is de-asserted using the MAXRATIO as its default divide ratio, the clock can be used for clocking the sampling of the clock ratio input.


The reset of a clock divider is a sensitive issue, typically the divider should output a clock at all times, so we can use this clock for all functionalities of the block. There is a difference between a synchronous reset block and an asynchronous reset block in the context of the clock divider reset.

For a block using synchronous reset, meaning that the clock needs to be toggling for the reset to bring the block to its initial state, the divider should be connected as follows:

  1. Connect the controlresetb signal to the block main reset signal, it will act within the divider as asynchronous reset , so even if the reset is asserted until the clock starts toggling it would still enable the divider to start driving using default configiration.
  2. Connect the divresetb to constant 1 (de-asserted), this means that the counter would start at some value and continue to count from there, for simulation purpose, you may need to artificially create a falling edge on this reset signal so the X values in the counter are cleared.

For a block using purely asynchronous reset, connect both divider reset signals to the asynchronous reset of the block, this will ensure proper divider startup without the need to create artificial edges for simulation purpose.

Test Items

Item name


Clock and reset

Check different orders of clock and reset, reset deasserted first, clock starts first check divider output valid value in each case

Divratio X

Check that when the divratio is connected to x, or changes to x, the divider stil continues to produce clock

Divratio 0

Check that divratio constant at 0 works which is an illegal case.


Check all divide ratios

Frequency change

Check all combinations of frequency changes

Controlclk from divclk

Connect controlclk to divclk, check divider starts at all above cases


Block integration diagram

clock divider physical application


The typical integration of the clock divider into a block design is shown in the above drawing.

Physical integration

At the physical integration stage, the divider should be placed at the block boundary, close to the reference clock input. The divclk output would become the clock source of the block and the controlclk can be connected to it and balanced as part of the block clock tree.

At timing closure, the refclk and control clock may be defined as asynchronous, but since there is a clear relation between them, the timing tool should not have issues with leaving this relation unconstrained. The divratio input timing is related to the controlclk, so at the context of the block this may be a simple same clock timing relation.