Daisy chain control and status bus

 
 
Verified

The Control and Status Registers daisy chain connectivity module is to connect a central logic (CPU, DMA controller) to multiple different blocks on a chip using daisy chained bus. The main advantages of daisy chain connectivity are the flexibility of adding new slaves (targets) and the low number of signals running long distance from the central logic to each of the target. The main disadvantage of the daisy chain approach is high access latency. The daisy chain system consists of a central controller block (master) which interfaces to CPU/DMA and several identical target (slave) blocks connected in daisy chains. Each target has an interface that could be connected to a local CSR block. The master supports up to 8 chains where the number of targets in each chain is limited only by the required maximal latency. The master can handle a large pre-defined number of outstanding transactions and is capable of rearranging the order of responses for transactions to different chains. This functionality allows out of order execution of accesses to the different chains and improves the overall performance. The proper transfer and response order is kept on CPU/DMA interfaces and on each target interface to its CSR block.

Block diagram

The below block diagram shows basic concept of CSR Daisy Chain bus:

Daisy-chain CSR system block diagram

 

Features

  • Asynchronous reset.
  • Parameterized chain number (1,2,...,8)
  • Parameterized target number
  • Parameterized data width
  • Parameterized address width
  • Parameterized max burst size
  • Parameterized max number of outstanding transfers
  • Parameterized reordering buffer memory depth
  • Parameterized depth of FIFOs in Master chain drivers
  • Parameterized depth of FIFOs in targets
  • Simple deep pipeline interface for CPU and DMA
  • Simple but flexible interface between target and user CSR block.
  • Posted write transfers from CPU and DMA (no responses, interrupt in case of error)
  • Internal arbitration between DMA and CPU access requests.
  • Support for out-of-order execution with response reordering.
  • Support for sequential or same-address bursts.
  • Interface to reordering buffer memory, so any memory elements can be used

Deliverables

  • Verified RTL code
  • Access to detailed design documentation
  • 1 year support and customization service.

 

Target parameters table

Parameter

Valid values

description

TARGET_ID

natural

Target index in system

DATA_WIDTH

natural

Width of data

ADDR_WIDTH

natural

Width of address

SIZE_WIDTH

natural

Width of burst size

TGTID_SIZE

natural

Number of bits to store TARGET_ID (depends on number of targets in whole system)

TRAN_FIFO_DEPTH

natural >= 4

Depth of transaction FIFO typically 4 entries

DATA_FIFO_DEPTH

natural >= 4

Depth of write data FIFO typically 64 entries

RESP_FIFO_DEPTH

natural >= 4

Depth of response FIFO typically 64 entries

 

SLOT_WIDTH is a parameter which is a function of the other chain field sizes.

 

Target interface table

Signal name

Direction/width

description

resetn

Input

Reset signal (active low)

clock

Input

Clock signal (active rising edge)

dcb_in

Input [SLOT_WIDTH-1:0]

Daisy chain message input

dcb_out

Output [SLOT_WIDTH-1:0]

Daisy chain message  output

address

Output [ADDR_WIDTH-1:0]

Address for CSR block

cmd_req

Output [1:0]

Command for CSR  block (read/write/idle)

cmd_ack

Input

Command acknowledge

same_addr

Output

Flag indicating burst from/to single address

tran_size

Output [SIZE_WIDTH-1:0]

Number of remaining chunks in current burst

read_data

Input [DATA_WIDTH-1:0]

Data read from CSR  block

write_data

Output [DATA_WIDTH-1:0]

Data to write to CSR  block

tran_valid

Input

Valid read data or data written successfully (acknowledge for data phase of the transfer)

tran_error

Input

Incorrect transfer indication

interrupt

Input

Interrupt request

Target overview

Several target blocks connected together create a chain. Each target monitors the target ID field of the messages moving through the chain. If a message is addressed to the target it is removed from the chain (by clearing VALID flag) and stored in one of the target input FIFOs. If the target identifies that the current message is not addressed to it, it allows the message to move forward to next target in the chain. After execution of a transfer on CSR block interface appropriate responses are generated by the target. The responses are stored in response FIFO and put into the chain whenever any unused slot is detected. The response will continue through the chain and eventually return to the master. Each response is than sent by the master to the CPU or DMA interface.

Burst types

The target block supports 2 types of burst transfers. Sequential burst where each following address is an increment of the previous one and 'same address' burst, where address does not change during entire transfer. The same address burst type may be used for accessing peripherals or for accessing FIFO type data structures within the block.

Message types

Each message moving through the chain has a valid bit, indicating whether the content of the message is valid. Each target would monitor this bit to verify the transaction is valid. Each valid message can be one of 3 types: transfer request, write data or response.

Additionally transfer requests and write data messages can have RETRY flag. The response message might be one of 3 types: OK, ERROR or INTERRUPT.

For read burst an OK response is generated for each read data chunk returned to the master and for write transfers only one OK response is generated after all data are successfully written to CSR block. In case of error signaled by CSR block the currently executed burst is canceled and ERROR response is send to the chain. If the ERROR occurs during a write burst, it may be possible that only part of the burst was written. 

The below table summarizes the types of transfers available on the daisy chain bus.

Type

Applies to

Description

RTRY

CMD

When a command cannot be accepted by the target it will continue as RTRY and the master will re-send it to the chain.

ERROR

RESP

When the block indicates a read transaction is complete without all data chunks returned or a write transaction did not complete correctly. Master would report error. Target will abort the rest of the transaction.

OK

RESP

RDDATA

Generated for each read chunk and as a response once all write burst is complete.

INTERRUPT

RESP

Used by the target and block to issue interrupt request to the master.

RD

CMD

Write transaction either single or burst

WR

CMD

Read transaction either single or burst

WRDATA

WRDATA

Write data transfer from the Master to the target.

Overflow prevention

The execution of transactions on the CSR block may be slow. Therefore, in the case when target identifies that current message is addressed to it but there is no free space to store it in transfer or write data FIFOs, the message cannot be accepted. In such case the message continues moving through the chain, but gets an additional RETRY flag. Such message will return to chain master, which will identify the RETRY flag and re-send message to the chain. The target registers the details of first retried message and retries all further messages until the registered one is back and is accepted. This behavior allows the target to prevent overflow while keeping the original execution order on CSR block interface.

Interrupts handling

The CSR block can issue interrupt request to master, targeted for the CPU. The Interrupt vector is issued on read data port when the target requests an interrupt. The interrupt vector may contain information about the interrupt and its content is part of the interrupt protocol between the CSR block and the CPU. The Interrupt response is sent to master as fast as possible, bypassing any waiting responses in the target response queue. The interrupt is sent as a special response message which does not correspond to any transfer and goes right through the master transfer re-ordering mechanism. In response to the interrupt, the CPU can access the CSR block to perform an action or read a status register.

CSR block interface

Interface between target and CSR block consists of a 2-stage pipeline interface with independent handshake for command and data phase.

The cmd_req is defined as

“00” - IDLE,

“10” - WRITE,

“01” - READ,

“11” is not supported.

Each transfer has command phase and data phase. There is separate command phase and data phase for each chunk of burst. The command phase finishes while cmd_ack is asserted, data phase finishes while tran_valid or tran_error is asserted. The signals tran_valid or tran_error for current transfer cannot be asserted at the same time when cmd_ack is asserted for this transfer, it must have a delay of at least one clock cycle. For write transfers the write data must be valid during command phase (in the same time when address and cmd_req). For read transfers the read data is valid while tran_valid is asserted. There is only one outstanding transfer, while command is accepted and data phase for previously accepted command is not finished yet (waiting for tran_valid) the target will issue idle transfer while waiting for tran_valid. CSR block might be aware of bursts (observe tran_size & same_addr) for improving performance or timing but does not have to as each burst chunk can be considered as a separate transfer on the CSR to block interface. Signals cmd_ack as well as tran_valid/tran_error for idle transfers are ignored by the target.

The following waveform shows scenarios of the CSR target block interface.

CSR target to block interface waveform

 

Master Block diagram

daisy-chain CSR master block diagram

 

Master parameters table

Parameter

Valid values

description

CHAIN_NUM

1 – 8

Target index in system

TARGET_NUM

natural

Number of targets in all chains

DATA_WIDTH

natural

Width of data

ADDR_WIDTH

natural

Width of address

SIZE_WIDTH

natural

Width of burst size

TRAN_MAX_NUM

natural >= 4

Maximum number of outstanding transactions (transfers, not chunks)

MEMORY_DEPTH

natural >= 16

Response buffer memory depth

DRV_TRAN_DEPTH

natural >= 4

Depth of chain driver transaction FIFO

DRV_DATA_DEPTH

natural >= 4

Depth of chain driver write data FIFO

DRV_RESP_DEPTH

natural >= 4

Depth of chain driver response FIFO

 

INTR_WIDTH - Width of interrupt status is locally calculated

SLOT_WIDTH – width of Daisy-chain width is locally calculated

MEM_ADDR_SIZE – the address size of the response reordering buffer memory – internally calculated.

MEM_DATA_SIZE – the data size of the response re-ordering buffer, internally calculated

 

Master interface table

Signal name

Direction/width

description

resetn

Input

Reset signal (active low)

clock

Input

Clock signal (active rising edge)

cpu_tran_req

Input [1:0]

CPU interface transfer request

cpu_tran_ack

Output

CPU interface transfer acknowledge

cpu_tran_addr

Input [ADDR_WIDTH-1:0]

CPU interface address

cpu_tran_size

Input [SIZE_WIDTH-1:0]

CPU interface burst size

cpu_tran_type

Input

CPU interface burst type (seq / same addr)

cpu_write_data

Input [DATA_WIDTH-1:0]

CPU interface write data

cpu_read_data

Output [DATA_WIDTH-1:0]

CPU interface read data

cpu_wdata_valid

Input

CPU interface write data valid

cpu_wdata_ack

Output

CPU interface write data acknowledge

cpu_rdata_valid

Output

CPU interface read data valid

cpu_rdata_error

Output

CPU interface read data error

cpu_rdata_ack

Intput

CPU interface read data acknowledge

dma_tran_req

Input [1:0]

DMA interface transfer request

dma_tran_ack

Output

DMA interface transfer acknowledge

dma_tran_addr

Input [ADDR_WIDTH-1:0]

DMA interface address

dma_tran_size

Input [SIZE_WIDTH-1:0]

DMA interface burst size

dma_tran_type

Input

DMA interface burst type (seq / same addr)

dma_write_data

Input [DATA_WIDTH-1:0]

DMA interface write data

dma_read_data

Output [DATA_WIDTH-1:0]

DMA interface read data

dma_wdata_valid

Input

DMA interface write data valid

dma_wdata_ack

Output

DMA interface write data acknowledge

dma_rdata_valid

Output

DMA interface read data valid

dma_rdata_error

Output

DMA interface read data error

dma_rdata_ack

Intput

DMA interface read data acknowledge

interrupt_req

Output

Interrupt request

interrupt_ack

Intput

Interrupt acknowledge

interrupt_status

Output [INTR_WIDTH-1:0]

Interrupt status

mem_write_en

Output

Response buffer memory write enable

mem_write_addr

Output [MEM_ADDR_SIZE-1:0]

Response buffer memory write address

mem_write_data

Output
[MEM_DATA_SIZE-1:0]

Response buffer memory write data

mem_read_en

Output

Response buffer memory read enable

mem_read_addr

Output [MEM_ADDR_SIZE-1:0]

Response buffer memory read address

mem_read_data

Intput
[MEM_DATA_SIZE-1:0]

Response buffer memory read data

chain_0_out

Output [SLOT_WIDTH-1:0]

Output for daisy chain 0

chain_0_in

Input [SLOT_WIDTH-1:0]

Input from daisy chain 0

chain_1_out

Output [SLOT_WIDTH-1:0]

Output for daisy chain 1

chain_1_in

Input [SLOT_WIDTH-1:0]

Input from daisy chain 1

chain_2_out

Output [SLOT_WIDTH-1:0]

Output for daisy chain 2

chain_2_in

Input [SLOT_WIDTH-1:0]

Input from daisy chain 2

chain_3_out

Output [SLOT_WIDTH-1:0]

Output for daisy chain 3

chain_3_in

Input [SLOT_WIDTH-1:0]

Input from daisy chain 3

chain_4_out

Output [SLOT_WIDTH-1:0]

Output for daisy chain 4

chain_4_in

Input [SLOT_WIDTH-1:0]

Input from daisy chain 4

chain_5_out

Output [SLOT_WIDTH-1:0]

Output for daisy chain 5

chain_5_in

Input [SLOT_WIDTH-1:0]

Input from daisy chain 5

chain_6_out

Output [SLOT_WIDTH-1:0]

Output for daisy chain 6

chain_6_in

Input [SLOT_WIDTH-1:0]

Input from daisy chain 6

chain_7_out

Output [SLOT_WIDTH-1:0]

Output for daisy chain 7

chain_7_in

Input [SLOT_WIDTH-1:0]

Input from daisy chain 7

Master overview

The Daisy-chain system central controller block (master) is responsible for assigning transfers requested from external CPU and DMA interfaces to proper chains and for returning the appropriate responses to the CPU and DMA interfaces. Up to TRAN_MAX_NUM outstanding transfers could be concurrently executed in the chains and several additional transfer requests could be captured and stored in FIFOs of master. Decoding address of transfer allows master to assign the transfer to the appropriate target in the appropriate chain. Messages are then sent to the chains and responses for those transfers are collected in a separate FIFO per each chain. The master supports out-of-order execution of transfers assigned to different targets; therefore, the order of responses must be rearranged to fit the original request's order. This task is performed in the response reordering buffer logic. The re-ordering buffer implementation is based on linked list queue, allowing for transactions of small and large sizes. Responses are then rewritten from a FIFO per chain to common reordering buffer. Reordered responses are returned to CPU / DMA interfaces in the original order they were requested. Only the read responses and interrupts are returned to the CPU or DMA. OK responses for write transfers are not forward to the CPU and ERROR responses for writes are signalized to external logic through special interrupt type. Interrupts coming from chains are not reordered and are signalized to external logic in the order they came to master.

CPU / DMA interfaces

CPU and DMA external interfaces are deep pipeline interfaces and can accept several transfer requests before returning responses. It allows for maximal overall throughput in daisy chain system which has large response latency by definition. The cpu_tran_req and dma_tran_req are defined as “00” - IDLE, “10” - WRITE, “01” - READ, “11” - NOT SUPPORTED.
CPU / DMA interfaces has dual handshake on command, data and response signals. For example cpu_tran_req is accepted by cpu_tran_ack, cpu_write_data is accepted by cpu_wdata_ack while active cpu_wdata_valid and cpu_read_data is accepted by cpu_rdata_ack while cpu_rdata_valid or cpu_rdata_error are asserted. This allows both sides (daisy chain master and external CPU/DMA device) to stall the interface until ready to acceptance of new request/data/response.

Overflow prevention

Because the daisy chain system is based on FIFO queues it is completely protected against overflow on various stages. The structure of the reordering buffer allows for no more than TRAN_MAX_NUM outstanding transfers to be concurrently executed, limiting the potential overflow in the different elements. The message RETRY mechanism prevents targets which are not ready to accept new message from causing overflow in the chain. When the master receives a RETRY response, it re-sends the command and stops initiating new messages until all retried messages are accepted by targets. This behavior allows for increased number of free slots moving through the chain and allows more bandwidth for potential pending responses. Additionally, the master would send transfer request to chain only if all outstanding responses from this chain would surely fit into the response per chain FIFO preventing FIFO overflow. Additional protection limits the overall number of outstanding responses to the depth of reordering buffer.     

Interrupts handling

The CSR block can issue interrupt request to the CPU through the chain. The Interrupt vector is delivered to the master with the interrupt response. The interrupt vector may contain information about the interrupt and its content is part of the interrupt protocol between the CSR block and the CPU. The Interrupt response is sent to master as fast as possible, bypassing any waiting responses in the target response queue. The interrupt is sent by the master to the CPU as a special response message which does not correspond to any transfer and goes right through the master transfer re-ordering mechanism. In response to the interrupt, the CPU can access the CSR block to perform an action or read a status register.

Address configuration

The address map of the daisy chain system is configured by a special include file “dcbus_addressmap.v”. Some parts of this file must be modified according to actual number of targets in the chains and address map. An example of “dcbus_addressmap.v” configuration file is below:


/* example of configuration file */

// set bellow CHAIN_SIZE_* parameter
// to number of targets in each chain
parameter CHAIN_SIZE_0 = 1;
parameter CHAIN_SIZE_1 = 2;
parameter CHAIN_SIZE_2 = 2;
parameter CHAIN_SIZE_3 = 0;
parameter CHAIN_SIZE_4 = 0;
parameter CHAIN_SIZE_5 = 0;
parameter CHAIN_SIZE_6 = 0;
parameter CHAIN_SIZE_7 = 0;

// set appropriate values for above signals
// depending on address map in your project
// remember that target numbers must be
// continuous from 0 to TARGET_NUM-1 and
// must start from first target in chain_0
// for example if we have 3 chains,
// 1 target in chain 0, and 2 targets in
// chains 1 and 2
// target's ID would be
// chain 0 target 0 - 0
// chain 1 target 0 - 1
// chain 1 target 1 - 2
// chain 2 target 0 - 3
// chain 2 target 1 - 4
// there is one restriction about address
// it is not allowed that address belongs
// to more than one target
initial
    begin
        // target 0
        cfg_addr_low[0]     = 8'h00;
        cfg_addr_high[0]    = 8'h1F;
        cfg_chain_idx[0]    = 0;
        // target 1
        cfg_addr_low[1]     = 8'h70;
        cfg_addr_high[1]    = 8'hF0;
        cfg_chain_idx[1]    = 1;
        // target 2
        cfg_addr_low[2]     = 8'h2C;
        cfg_addr_high[2]    = 8'h35;
        cfg_chain_idx[2]    = 1;
        // target 3
        cfg_addr_low[3]     = 8'h40;
        cfg_addr_high[3]    = 8'h4F;
        cfg_chain_idx[3]    = 2;
        // target 4
        cfg_addr_low[4]     = 8'h50;
        cfg_addr_high[4]    = 8'h6F;
        cfg_chain_idx[4]    = 2;
    end

/* end of configuration file example */

Daisy Chain slot fields

Each message in daisy chain is one word of SLOT_WIDTH bits wide. The meaning of fields in message slightly differs depending on message type. Below is description of the fields. 
 

Transaction request fields:

Size of field      

Description

2

slot type ( valid / free )

2

message type  ( tran / data / resp )

2

response type ( OK / ERR / RTRY / INTR )

1

command type  ( write – 1 / read – 0 )

1

transfer type ( sequential – 0 / same – 1 )

TARGET_ID_SIZE 

target ID

TRANS_ID_SIZE 

transfer ID

SIZE_WIDTH     

burst size (in words )

ADDR_WIDTH   

start address

 

 

Write data fields:

Size of field      

Description

2

slot type ( valid / free )

2

message type  ( tran / data / resp )

2

response type ( OK / ERR / RTRY / INTR )

1

command type  ( write – 1 / read – 0 )

1

transfer type ( sequential – 0 / same – 1 )

TARGET_ID_SIZE 

target ID

TRANS_ID_SIZE 

transfer ID

SIZE_WIDTH    

burst size (in words )

DATA_WIDTH

data to write

 

 

Response fields:

Size of field      

Description

2

slot type ( valid / free )

2

message type  ( tran / data / resp )

2

response type ( OK / ERR / RTRY / INTR )

1

command type  ( write – 1 / read – 0 )

1

transfer type ( sequential – 0 / same – 1 )

TARGET_ID_SIZE 

target ID

TRANS_ID_SIZE 

transfer ID

SIZE_WIDTH     

burst size (in words )

DATA_WIDTH

read data

 

 

Data and address fields are placed in [DATA_WIDTH-1:0] or [ADDR_WIDTH-1:0] bits. The rest of fields is placed starting from the MSB. For example 'slot type' field in placed on [SLOT_SIZE-1:SLOT_SIZE-2], message type on [SLOT_SIZE-3:SLOT_SIZE-4], and so on.

 

 

Test Items


The below table summarizes the test items that were checked for the Daisy Chain Bus

Item name

Description

single reads, no DMA, no error responses, no handshake delays on interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

single reads, no DMA, no error responses, random handshake delays on CPU interface, no delays on CSR block interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

single reads, no DMA, no error responses, random handshake delays on CSR blocks interfaces, no delays on CPU interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

single reads, no DMA, no error responses, random handshake delays on CPU interface, random handshake delays on CSR blocks interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

single writes, no DMA, no error responses, no handshake delays on interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

single writes, no DMA, no error responses, random handshake delays on CPU interface, no delays on CSR block interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

single writes, no DMA, no error responses, random handshake delays on CSR blocks interfaces, no delays on CPU interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

single writes, no DMA, no error responses, random handshake delays on CPU interface, random handshake delays on CSR blocks interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

burst reads, no DMA, no error responses, no handshake delays on interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

burst reads, no DMA, no error responses, random handshake delays on CPU interface, no delays on CSR block interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

burst reads, no DMA, no error responses, random handshake delays on CSR blocks interfaces, no delays on CPU interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

burst reads, no DMA, no error responses, random handshake delays on CPU interface, random handshake delays on CSR blocks interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

burst writes, no DMA, no error responses, no handshake delays on interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

burst writes, no DMA, no error responses, random handshake delays on CPU interface, no delays on CSR block interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

burst writes, no DMA, no error responses, random handshake delays on CSR blocks interfaces, no delays on CPU interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

burst writes, no DMA, no error responses, random handshake delays on CPU interface, random handshake delays on CSR blocks interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, no DMA, no error responses, no handshake delays on interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, no DMA, no error responses, random handshake delays on CPU interface, no delays on CSR block interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, no DMA, no error responses, random handshake delays on CSR blocks interfaces, no delays on CPU interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, no DMA, no error responses, random handshake delays on CPU interface, random handshake delays on CSR blocks interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, no DMA, error responses, no handshake delays on interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, no DMA, error responses, random handshake delays on CPU interface, no delays on CSR block interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, no DMA, error responses, random handshake delays on CSR blocks interfaces, no delays on CPU interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, no DMA, no error responses, random handshake delays on CPU interface, random handshake delays on CSR blocks interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, DMA, error responses, no handshake delays on interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, DMA, error responses, random handshake delays on CPU interface, no delays on CSR block interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, DMA, error responses, random handshake delays on CSR blocks interfaces, no delays on CPU interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, DMA, no error responses, random handshake delays on CPU interface, random handshake delays on CSR blocks interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces

random reads and writes, DMA, error responses, interrupts, no handshake delays on interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces, check interrupt handling

random reads and writes, DMA, error responses, interrupts, random handshake delays on CPU interface, no delays on CSR block interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces, check interrupt handling

random reads and writes, DMA, error responses, interrupts, random handshake delays on CSR blocks interfaces, no delays on CPU interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces, check interrupt handling

random reads and writes, DMA, no error responses, interrupts, random handshake delays on CPU interface, random handshake delays on CSR blocks interfaces

Check correctness of transfer details and order on both CPU/DMA and CSR block interfaces, check interrupt handling

RETRY functionality

Check correctness of retried messages handling

Overflow prevention

Check correctness of response overflow prevention in chain driver

Max transaction number

Check correctness of assurance that no more than TRAN_MAX_NUM transaction is processed concurrently

Unique transaction ID

Check correctness of assurance that transaction ID of all currently processed transactions is unique (otherwise there might be errors in reordering)

Max expected responses

Check correctness of assurance that all currently expected responses could fit into reordering buffer

Write error interrupts

Check if error response on CSR block interface is transformed into interrupt

Incorrect address errors

Check if transfer requests for incorrect (out pf space) addresses have appropriate error responses (or error interrupts in case of writes)


Each of above items was tested for various configurations of daisy chain system. These configurations varied in: number of used chains, number of targets, address maps, data width , address width, size width, depth of FIFOs, max number of outstanding transfers, depth of reordering buffer. Most of tests were randomized and self-checking.

Assumptions

The following assumptions and rules should be followed:

  1. Up to 8 chains is supported.
  2. All FIFO depth parameters must be set for at least 4.
  3. Memory for linked list buffer must be 1 cycle read latency.
  4. Address map of targets should be defined by modification parts of “dcbus_addressmap.v”
  5. Target numeration must be continuous starting from 0 for first target in chain 0.
  6. TRAN_MAX_NUM parameter must be set to at least 4

 

Usability

Daisy chained bus is useful for applications where there is a need of connection multiple logic blocks with central control logic (CPU/DMA) and latency of transfer is not critical. The advantages of daisy chained bus is flexibility of adding new slaves and low number of signals running long distance from CPU to destination block.