Fifos

  • Interconnect Interface FIFO

    An interface FIFO serves to facilitate chip level integration by providing a full handshake interface between two block that is sampled in both directions. sampling signals in both sending and receiving blocks is a way of reducing the complexity of chip level timing closure.

  • Basic FIFO

    FIFO is an acronym for First In, First Out data organization method. FIFOs are widely used in logic design for buffering, queuing and management of rate, priorities and flow control in data applications. A FIFO consists of a read pointer and a write pointer, pointing to entries in a storage array typically, made of flip-flops.

  • Generic FIFO

    A “generic FIFO” is a reference name to the simple type of synchronous FIFOs, where the memory array is based of flip-flops and the pointers and status (full, empty, almost full etc.) are generated using counters or pointers logic.

  • Memory based FIFO

    A “Memory Based FIFO” is a reference name to the simple type of synchronous FIFOs, where the memory array is based on an embedded memory and the pointers and status (full, empty, almost full etc.) are generated using counters or pointers logic.

  • Gearbox width rate converter FIFO

    A Gearbox FIFO is a component which allows the conversion of data bus width from input to output. Data of W width, written to FIFO can be read, depending on configuration, as W*N or W/N width vectors where N is natural number providing the rate of read and write match the required data bus width change. The component supports three versions of clocking and rate modes.

  • MUltiple FIFO in one memory array

    The Multiple FIFO component is a device which allows hosting multiple FIFO queues of the same depth within a single memory structure. Only one FIFO can be written and read in each clock cycle. Each load or extract request is qualified with the number of the FIFO to which it refers.