Gearbox width rate converter fifo

 
 
Verified

A Gearbox FIFO is a component which allows the conversion of data bus width from input to output. Data of W width, written to FIFO can be read, depending on configuration, as W*N or W/N width vectors where N is natural number providing the rate of read and write match the required data bus width change. The component supports three versions of clocking and rate modes.

  1. Using the same clock on both write and read sides.
  2. Using edge aligned synchronous clocks on both sides, where the clock frequency matches the required bus width change, keeping data rate equal on both sides.
  3. Using asynchronous clocks where the rates of the clocks match the required data bus width change. The gearbox FIFO behaves in this case as standard non flow-through FIFO with a read latency equal 1 clock cycle.

The Gearbox FIFO can be used in multiple applications allowing smooth conversion between synchronous and asynchronous clock domains. Typical usage would be within system interfaces, allowing independent clock domains to safely transfer data between them.

Block diagram

The below block diagram shows basic concept of gearbox FIFO component:


gearbox FIFO block diagram

 

Features

  • Parametrized FIFO width and depth.
  • Parametrized width conversion mode 1:N or N:1.
  • Parametrized width conversion ratio 1,2,...,8.
  • Full, empty and almost full status flags.
  • Three modes of clocking slectable through parameter setting.
  • Support for adding sampling stages for timing on the memory interface.
  • One cycle memory array read latency in all modes.
  • External memory interface.

Additional features

  • Synchronous and asynchronous reset

Deliverables

  • Verified RTL code
  • Access to detailed design documentation
  • 1 year support and customization service

 

Parameters table

Parameter

Valid values

description

FIFOWIDTH

natural

Width of wider data, width of FIFO.

FIFODEPTH

natural

Depth of FIFO (in words)

 

 

 

RATIOMODE

0,1

Type of conversion
0 – 1:N – narrow to wide

1 – N:1 – wide to narrow

SIZERATIO

1 – 8

Width conversion ratio.

OPERATION

0,1,2

Type of clocking
0 – same clock

1 – synchronous clocks with frequency ratio same as SIZERATIO
2 – asynchronous clocks with matching frequency

RDLATENCY

1,3

Memory read latency,

ALMOSTFULL_DEPTH

0-(DEPTH-2)

Almost full flow control indication depth

 

Interface table

Signal name

Direction/width

description

resetb

Input

Active low reset signal

wr_clk

Input

Write side clock signal

rd_clk

Input

Read side clock signal

load_data

Input
[FIFOWIDTH-1:0]

Data loaded to FIFO

load

Input

Load command request

extract_data

Output
[FIFOWIDTH-1:0]

Data extracted from FIFO

extract

Input

Extract command request

fifo_full

Output

Full status flag

fifo_empty

Output

Empty status flag

fifo_almostfull

Output

Almost full status flag

mem_wr_en

Output

Memory write strobe

mem_wr_addr

Output

[LOG2DEPTH-1:0]

Memory write address

mem_wr_data

Output
[FIFOWIDTH-1:0]

Memory write data

mem_rd_en

Output

Memory read strobe

mem_rd_addr

Output

[LOG2DEPTH-1:0]

Memory read address

mem_rd_data

Input
[FIFOWIDTH-1:0]

Memory read data

FIFO

The gearbox component is a type of FIFO queue designed specifically to facilitate data rate conversion. FIFO is an acronym for First In First Out. This expression describes the principle of queue, data leaves the queue in the order they arrive. FIFO queues are commonly used in electronic circuits for synchronization, buffering and flow control.

Width conversion

The main feature of gearbox device is ability to convert data widths between write and read sides of FIFO. Depending on parameters, the gearbox can convert write side data vector of width W to a width of W*N or W/N wide vectors on the read side. Conversion is always made in way that the first word of narrower side is placed on least significant part of wider side. For example, for conversion from 8-bit bus to 32-bit bus of subsequent 8-bit words AA, BB, CC, DD the 32-bit word will be DDCCBBAA. Both, the conversion mode and size ratio are set through parameters. For the opposite conversion, the same ordering rule applies.

Write side words

Read side words

8’hAA

32’hDDCCBBAA

8’hBB

8’hCC

8’hDD

Status flags

Similar to other FIFO components, the gearbox FIFO has three status flags. Empty flag means that there is no valid data in queue. Full flag means that there is no free space left in queue and no data could be load before extracting at least one word. Almost full flag indicates that there is free space for a number of words equal to ALMOSTFULL_DEPTH word of data.

Gearbox FIFO Clocking

The gearbox FIFO supports three types of clocking schemes. One of them is the same clock on both write and read sides. Second mode is with edge aligned synchronous clocks with frequency ratio matched to width conversion ratio. Internal FIFO in the case of synchronous different frequency clocks is clocked by faster clock. The third mode is asynchronous clocks on write and read side with matching rates. For the asynchronous clocks mode, the rates of data on both sides must match the bus width change in order to prevent FIFO overflow. When the clocks are sourced from completely unrelated sources, it is advisable to have a certain speed-up of the read clock over the write clock ensuring that FIFO overflow due to frequency drift will not occur. For more information and best-practices on this issue please refer to the application section.

Gearbox Memory interface

The gearbox FIFO is designed to work with an external 2 port (1 read/1 write) memory structure with 1 cycle of read latency. The component supports the option to add an additional sampling stage on the memory control and data signals for the purpose of improving timing. This option is selectable through a parameter. The gearbox FIFO will behave the same way with the additional sampling stages, allowing for late changes without functional Impact.

Read Latency

The latency of the extracted data in relation to the extract command is always one read clock cycle regardless of the additional memory latency introduced for timing purposes or the internal logic. The latency is constant and independent on clocking scheme or conversion mode. Once the extract command is asserted, the data will be available on the same cycle for sampling by the external logic.

Test Items

The below table summarizes the test items that were checked for the gearbox FIFO

Item name

Description

Reset functionality

Check if all flagshave proper initial values.

Full flag assertion.

Check correctness of full flag assertion.

Full flag deassertion.

Check correctness of full flag deassertion.

Almost full flag assertion.

Check correctness of almost full flag assertion.

Almost full flag deassertion.

Check correctness of almost full flag deassertion.

Empty flag assertion.

Check correctness of empty flag assertion.

Empty flag deassertion.

Check correctness of empty flag deassertion.

Data order and correctness.

Check, if the order of data extracted from FIFO corresponds to the order they were loaded to queues with respect to width conversion.


Each of above items were tested for all clocking modes for different sets of fifo width, depth with various RATIOMODE and SIZERATIO values.

Assumptions

The following assumptions and rules should be followed, those can be used as error indications:

1.    In synchronous clocks mode the frequency of the wider side clock must be SIZERATIO as slow as the narrower side clock.

2.    Memory must be 1 or 3 cycle read latency

Usability

Gearbox FIFO is suitable for all applications that require converting the width of data buses. It also could work as a standard 1:1 synchronous or asynchronous FIFO.