Generic fifo

 
 
SiliconProven

A “generic FIFO” is a reference name to the simple type of synchronous FIFOs, where the memory array is based of flip-flops and the pointers and status (full, empty, almost full etc.) are generated using counters or pointers logic.

There are two types of generic FIFOs, the Log2 FIFO is a FIFO designed for specific depths which are a power of 2, meaning 2, 4, 8, 16, 32…, 128.. Those would have a simplified set of pointers that are used also for generating the flow control indication empty and full. The Log2 FIFO type does not have the option for an almostful flow control signal, enabling easier integration into pipelines. The FIFO with almostfull or almostempty functionality can have any depth of the FIFO itself and the almostfull function. This makes it more robust for pipeline and other handshake applications. for the sampled data out FIFO, the data at the output is sampled for improved dataout timing. the sampling stage is enabled for sampling at a valid read from the FIFO therefore, the data at the output would remain constant between consecutive reads,keeping the last read data.

Block diagram

generic FIFO block diagram

 

Features

  • Single clock synchronous functionality
  • Asynchronous reset of FIFO pointers
  • Flip-flop based memory array
  • Parameter controlled depth
  • Parameter controlled width
  • Empty and full indications
  • Prevents load when FIFO is full
  • Prevents extract when FIFO is empty
  • Almost full indication with parameter selectable depth for flow control

Optional features

  • synchronous and asynchronous reset

Deliverables

  • verified RTL code
  • Access to detailed design documentation
  • 1 year support and customization service.

parameters table

Parameter

Valid values

description

WIDTH

 

FIFO width

DEPTH

any  depth

FIFO depth

ALMOSTFULL_DEPTH

up to the FIFO address

the almost full depth is the number of available entries in the FIFO when the almostfull flow control signal is asserted. a value of 3 for example, means that there are 3 available entries before the FIFO gets full.

ALMOSTEMPTY_DEPTH up to the FIFO address the almost empty depth is the number of full entries in the FIFO when the almostempty flow control signal is asserted. a value of 3 for example, means that there are 3 filled entries before the FIFO gets empty.

interface table

Signal name

Direction/width

description

clk

Input

Clock signal

resetb

Input

Active low reset signal, when asserted, pointers would return to zero and empty indication would be set

load

Input

Indicates the FIFO is to be written, will be ignored when FIFO is full and extract is de-asserted

extract

Input

Indicates a FIFO entry is to be read, will be ignored when FIFO is empty

empty

Output

Indication that the FIFO is empty. Extract operations are ignored while FIFO is empty

full

Output

Indication that the FIFO is full. Load operations are ignored while FIFO is full

datain

Input [WIDTH – 1:0]

Data input

dataout

Output [WIDTH – 1:0]

Data output

almostfull

output

the almostfull indication serves for flow control, it is asserted when the FIFO has ALMOSTFULL_DEPTH available entries or less

Almostempty

output

the almostempty indication serves for flow control, it is asserted when the FIFO has ALMOSTEMPTY_DEPTH remaining entries or less

Log2 FIFO functionality

The generic synchronous FIFO for log2 depths is designed with a flip-flop memory array and a set of read pointer and write pointer.

The FIFO reset functionality is either synchronous or asynchronous and should be used according to the overall reset policy of the instantiating device.

The status indications are implemented using a wrap-around bit in the pointers.

When the FIFO is full, simultaneous load and extract is supported, but care must be taken as the upstream logic has no indication whether the data has been loaded or dropped without evaluating the extract signal. For that reason, the typical application would mask the load signal with the full indication, preventing the simultaneous load and extract while the FIFO is full.

The FIFO depth and width are parameters that can be set to any valid value at instantiation.Additional parameter sets the width of the required address of the FIFO i.e., for a FIFO of depth 16, 4 bits would be required.

Generic FIFO should be used only for relatively small arrays where timing requirement can be met, for bigger arrays, a memory based FIFO should be used.

almost full FIFO functionality

The FIFO that includes the almost full flow control functionality would assert the almostfull signal some cycles before the FIFO gets full, this will allow the flow to be stopped further up the pipe. The FIFO would absorb the entries which are in flight so no data is lost. the ALMOSTFULL_DEPTH parameter should be set according to the number of sampling pipe stages before the FIFO.

The disadvantage of the almostfull comes where the FIFO is read, the flow control would be de-asserted only after there are ALMOSTFULL_DEPTH free entries in the FIFO. to prevent bubbles at the FIFO output and FIFO underruns, the FIFO depth should be at least double the size of the ALMOSTFULL_DEPTH so the it does not get empty before the new entries are loaded once the almostfull signal is de-asserted.

almost empty FIFO functionality

The FIFO that includes the almost empty flow control functionality would assert the almostempty signal some cycles before the FIFO gets empty, this will allow the flow to be stopped further down the pipe or can be used for other purposes like triggering upstream logic operation.

Load and extract functionality

generic FIFO

The load and extract operations of the FIFO impact the FIFO pointers.

When the load signal is asserted, the data on the datain is loaded into the position pointed by the write pointer and the pointer is then incremented by 1 to point to the next FIFO entry. If the FIFO full indication is asserted, and the extract signal is not asserted, the load operation would be ignored and the pointer would not be incremented.

Simultaneous load and extract operations to the FIFO when full indication is asserted will result is a write of the datain to the FIFO and a read to the dataout. The full indication will remain asserted in that case.

the below diagram shows the load and extract operations and the impact of them on the full and empty signals

generic FIFO load and extract functionality

In the above drawing, at time T1, the empty signal is de-asserted after the first write operation is complete. At T2, simultaneous load and extract operations are performed when the FIFO is full. The result is that the FIFO remains full as data D5 is written into the FIFO and D1 is read, at the same time.

At time T3, the last written entry is extracted from the FIFO and the empty signal is asserted.

almost full FIFO

for the FIFO with almostfull indication, the load and extract operations are basically the same, the below diagram shows the behavior of  a 4 deep FIFO with an ALMOSTFULL_DEPTH set to 1 entry.

generic FIFO almostful functionality

 

Reset

The fifo_generic_asyncrst uses asynchronous active low reset signal. Once asserted, the pointers would return to their default value of 0 and the FIFO empty signal would be asserted.

The reset operation has no impact on the content of the memory array itself.

The fifo_generic_syncrst uses synchronous active low reset signal. Once asserted, the pointers would return to their default value of 0 at the rising edge of the clock and the FIFO empty signal would be asserted.

The reset operation has no impact on the content of the memory array itself.

for the FIFO with sampled data output, the datout stage is reset so the FIFO actually outputs a value of 0 right after reset is de-asserted.

 

Test Items

the below table summarizes the test items that were checked for the generic FIFOs

some of the items are relevant only for specific examples.

Item name

Description

Reset functionality

Check reset assertion during operation, see that the pointers return to zero.

empty

Write to FIFO, check that FIFO empty indication is de-asserted.

Full functionality

Write to the FIFO the same number of entries as its depth, check that the full indication is asserted

Load when full

Load the FIFO when full indication is asserted, check that the loaded data is ignored and the FIFO ignores the load.

Simultaneous load and extract when full

Perform a simultaneous load and extract operations while the FIFO is full, see that both operations work, continue for multiple times, until written entry is read out.

Output sampling reset

Check that the dataout is zero after reset assertion

Output sampling

Check that dataout is reading one cycle after extract is asserted. Check that data is unchanged when extract is not asserted, regardless of load operations.

additional test items for almost full functionality

Item name

Description

Almost full assertion

Fill FIFO, see that the almostfull is asserted exactly ALMOSTFULL_DEPTH cycles before the full is asserted

almostfull de-assertion

Perform extract operation on a full FIFO, check that the almostfull is de-asserted after ALMOSTFULL_DEPTH entries are extracted.

 

Integration

Generic flop based FIFO should be used only for relatively small arrays where timing requirement can be met, for bigger arrays, a memory based FIFO should be used.

The integration of the FIFO into a pipeline design requires the attention to flow control indications. The FIFO empty signal should be used for signaling downstream logic the there is available data at the FIFO outout. the full indication should be used for signaling the upstream logic to stall the pipe so data is not lost.

The almostfull signal is designed to enable th FIFO to absorb few entries when pipe is stalled upstream. the number of entries that can be absorbed is equal to the ALMOSTFULL parameter used for instantiating the block. Care should be taken when selecting an almostfull parameter value and typically should not exceed half the fifo depth, in order to prevent bubbles when almostfull is released.

Timing considerations

Data  in

When looking at the timing considerations for datain signal, one should look into the fanout of each data bit. The data bits actually reach each and every entry of the FIFO. A timing issue may arise for FIFOs with high entry count.

Data out

The timing for datout in the typical FIFO results from the number of entries as well. For each data bit, an output multiplexer with the number of entries is created. The number of logical stages of the output select depends on the number of entries.

For a FIFO with sampled output, the output stage, results in a clean timing as all dataout bits are coming directly from flops.

Load and extract signals

The load signal of the FIFO needs to reach all flops of the FIFO, and the write pointer logic. Usually, the load signal would be most timing critical in such FIFO design. The extract signal typically reaches mainly the read pointer but since the FIFO can be written when simultaneous load and extract operations are done while the FIFO is full, the fanout of the extract signal is similar to that of the load signal.

Empty and full indications

The indications are calculated from the pointers by comparing the pointer bits.