Interconnect interface fifo

 
SiliconProven

An interface FIFO serves to facilitate chip level integration by providing a full handshake interface between two block that is sampled in both directions. sampling signals in both sending and receiving blocks is a way of reducing the complexity of chip level timing closure. The interface FIFO is actually a FIFO which is divided between two blocks where the sending side contains the logic for calculating the FIFO full and almostfull indications and the receiving side, contains the FIFO data storage and pointers logic. The Interface FIFO is used by integrating the sending part into one block and the recieving part into another block. the depth parameter on both instantiations should be the same for proper functionality.This component provides a verified verilog source code for an interface FIFO, which serves to facilitate chip level integration by providing a fully sampled handshake interface between two block that is sampled in both directions. sampling signals in both sending and receiving blocks is a way of reducing the complexity of chip level timing closure. The interface FIFO is actually a FIFO which is divided between two blocks where the sending side contains the logic for calculating the FIFO full and almostfull indications and the receiving side, contains the FIFO data storage and pointers logic. The Interface FIFO is used by integrating the sending part into one block and the recieving part into another block. the depth parameter on both instantiations should be the same for proper functionality.

Block diagram

Interface FIFO block diagram

Features

  • fully sampled interface between receiving and sending parts of the FIFO.
  • dedicated init signal, serves for resetting both FIFO sides, preventing issues that may result from difference in reset delay between the blocks.
  • Single clock synchronous functionality
  • A register array with parameterized width and depth, used for storing FIFO data
  • Parameter controlled depth, allowing to enlarge the array using the same code
  • Parameter controlled width,  allowing to enlarge the array using the same code
  • Empty and full indications
  • Prevents load when FIFO is full, load signal is ignored when full, unless extract signal is asserted simultaneously.
  • Prevents extract when FIFO is empty, extract signal is ignored if FIFO is empty, unless load is asserted simultaneously.
  • Parameter controlled almostfull functionality

Optional features

  • synchronous and asynchronous reset

Deliverables

  • verified RTL code
  • Access to detailed design documentation
  • 1 year support and customization service.

parameters table

parameters for typical Interface FIFO, the parameters apply to both the send and the receive sides of the FIFO except the ALMOSTFULL_DEPTH which applies to the send side only.

Parameter

Valid values

description

WIDTH

 

FIFO width

DEPTH

any  depth

FIFO depth

 

 

 

ALMOSTFULL_DEPTH

up to the FIFO address

the almost full depth is the number of available entries in the FIFO when the almostfull flow control signal is asserted. a value of 3 for example, means that there are 3 available entries before the FIFO gets full.

 

 

Send Side interface table

Signal name

Direction/width

description

clk

Input

Clock signal

resetb

Input

Active low reset signal, when asserted, pointers would return to zero and empty indication would be set

load

Input

Indicates the FIFO is to be written, will be ignored when FIFO is full and extract is de-asserted

l2e_load

Output

Indication that the FIFO is loaded, serves as a qualifier for the e2l_datain signal, will be blocked if FIFO full

e2l_extract

Input

Indication from the receive side that an entry has been extracted from the FIFO.

e2l_init

Input

Initialization signal, serves to clear the send side FIFO. This is done for the purpose of keeping coherence where the two blocks have different reset timing

full

Output

Indication that the FIFO is full. Load operations are ignored while FIFO is full

datain

Input [WIDTH – 1:0]

Data input

l2e_datain

Output [WIDTH – 1:0]

Data output from the send side to the receive side.

almostfull

output

the almostfull indication serves for flow control, it is asserted when the FIFO has ALMOSTFULL_DEPTH available entries or less

Receive Side interface table

Signal name

Direction/width

description

clk

Input

Clock signal

resetb

Input

Active low reset signal, when asserted, pointers would return to zero and empty indication would be set

l2e_load

input

Indication that the FIFO is loaded, serves as a qualifier for the e2l_datain signal.

e2l_extract

Output

 

Indication from the receive side that an entry has been extracted from the FIFO.

init

Input

initialization signal, serves to ensure both sides of the FIFO are reset simultaneously, preventing coherency issues.

e2l_init

Output

Initialization signal, serves to clear the send side FIFO. This is done for the purpose of keeping coherence where the two blocks have different reset timing

l2e_datain

Input [WIDTH – 1:0]

Data input from the send side to the receive side.

dataout

Output [WIDTH – 1:0]

Data output.

empty

Output

Indication that the FIFO is empty. Extract operations are ignored while FIFO is empty

Extract

Input

Indicates a FIFO entry is to be read, will be ignored when FIFO is empty

 

Interface FIFO functionality

The interface FIFO is based on the design of a generic register based FIFO. the receiving part includes a register array for storing the FIFO data, pointer management logic and some counters for generating the FIFO flow control signals

the implementation is independent of the register array depth so a change to the array  size, often required in late design stages, would only require as change to the depth or width parameters.

The FIFO depth and width are parameters that can be set to any valid value at instantiation providing the embedded memory instance is replaced accordingly.

Additional parameter sets the width of the required address of the FIFO i.e., for a FIFO of depth 8 to 16 entries, 4 bits would be required.

The FIFO reset functionality is either synchronous or asynchronous; and should be selected according to the overall reset policy of the instantiating device.

the Interface FIFO is designed to interface between blocks on the chip using a fully sampled interface signals, facilitating easier full-chip timing closure.

The trade-off is naturally by adding more logic. The Interface FIFO minimal depth for proper operation is 6 entries as the worst case scenario is when the FIFO is currently full and now the extract signal gets asserted.

The extract indication need to travel through the 2 cycles of the interface sampling on both sides and then impact the logic in the other side, enabling new loads to the FIFO, which will take one additional cycle

The new loaded data needs to travel through the interface between the blocks, taking 2 cycles and be written into the array which will take one cycle more. so the round trip took 6 cycles and in order to prevent the FIFO from underrun, the number of entries must be 6 or higher.

if the almostfull is used, twice the number of cycle for almostfull should be added to the minimal FIFO depth, as the first loaded data would only reach the FIFO once the number of almostfull entries have been extracted in addition to the delay of the data from the flow control point to the FIFO.

therefore, for an interface FIFO with 2 cycles of almostfull, the minimal FIFO depth is 10 entries.

the below drawing shows this example.

note that it takes 2 cycles for the almost full to be de-asserted providing the extract signal remains asserted.

Interface FIFO round trip diagram

almost full functionality

The FIFO type that includes the almost full flow control functionality would assert the almostfull signal few cycles before the FIFO gets full, this will allow the flow to be stopped further up the pipe.

The FIFO would absorb the entries which are in flight so no data is lost. the ALMOSTFULL_DEPTH parameter should be set according to the number of sampling pipe stages before the FIFO.

The disadvantage of the almostfull comes where the FIFO is read, the flow control would be de-asserted only after there are ALMOSTFULL_DEPTH free entries in the FIFO. to prevent bubbles at the FIFO output and FIFO underruns, the FIFO depth should be at least double the size of the ALMOSTFULL_DEPTH so that it does not get empty before the new entries are loaded.

Test Items

the below table summarizes the test items that were checked for the Interface FIFOs

basically, the two parts together act as a simple generic FIFO.

some of the items are relevant only for specific examples.

Item name

Description

Reset functionality

Check reset assertion during operation, see that the pointers return to zero.

empty

Write to FIFO, check that FIFO empty indication is de-asserted.

Full functionality

Write to the FIFO the same number of entries as its depth, check that the full indication is asserted

Load when full

Load the FIFO when full indication is asserted, check that the loaded data is ignored and the FIFO ignores the load.

Simultaneous load and extract when full

Perform a simultaneous load and extract operations while the FIFO is full, see that both operations work, continue for multiple times, until written entry is read out.

check for under-run

at FIFO full, assert constantly load and extract for a period longer than the FIFO depth, expect first few loads to be dropped but the FIFO should never under-run causing bubbles at the output.

Almost full assertion

Fill FIFO, see that the almostfull is asserted exactly ALMOSTFULL_DEPTH cycles before the full is asserted

almostfull de-assertion

Perform extract operation on a full FIFO, check that the almostfull is de-asserted after ALMOSTFULL_DEPTH entries are extracted.

 

assumptions

the following assumptions and rules should be followed, those can be used as error indications:

  1. The send side FIFO should not have the sampled extract signal from receive side asserted when the status counter is 0
  2. The receive side should not be getting a load signal when the FIFO is full. 

Usability

The Interface FIFO is designed to be used at a block boundary where its advantages are:

  1. Enable bidirectional sampling of all signals between two blocks while keeping flow control available.
  2. Easy integration into both blocks as the send and receive block act as a FIFO in both ends.
  3. Simple depth and width control through parameters.
  4. Clearly defines the interface between the blocks, allowing parallel development and independent verification

Care must be taken in the following issues:

  1. Both sides must be configured to the same DEPTH, failure to do so will result in coherency issues.
  2. Large differences in reset de-assertion between the two sides may result in coherency issues as the receive side is in reset while the send side starts loading data. The init signal prevents this issue to some extent but some issues may still arise in different scenarios. The way to overcome this problem is to safely de-assert the init signal long after the reset is de-asserted, this will ensure both sides are kept empty until a common point in time where the send section starts responding to incoming loads after the receive side is ready.

Timing considerations

Data  in

datain signal is sampled directly at the send side flops so there should not be any timing issue.

Data out

The timing for dataout in the register array FIFO so the output mux of the FIFO should beconsidered for timing.

Load and extract signals

The load and extract signal of each side the FIFO needs to reach all the control logic, pointers, counters and bypass control logic, those signal may be timing critical and should be considered.

Empty and full indications

The indications are calculated from the FIFO status counter, going only through simple comparators.