Memory based fifo

 
 
SiliconProven

A “Memory Based FIFO” is a reference name to the simple type of synchronous FIFOs, where the memory array is based on an embedded memory and the pointers and status (full, empty, almost full etc.) are generated using counters or pointers logic.

The memory based FIFO can be used where a large storage is required for a FIFO while keeping the characteristics of a pipeline FIFO. The meaning is that whan the FIFO is empty; there is a one cycle delay from FIFO load to FIFO extract. This enables integration of the FIFO into a pipeline with practically no changes to the pipeline behavior.

 

Block diagram

Memory based FIFO block diagram

 

Features

  • Single clock synchronous functionality
  • two port embedded memory array with 1 read port and 1 write port, used for storing data
  • Parameter controlled depth, allowing to enlarge the memory array using the same code
  • Parameter controlled width,  allowing to enlarge the memory array using the same code
  • Empty and full indications
  • Prevents load when FIFO is full, load signal is ignored when full, unless extract signal is asserted simultaneously. This feature can be disabled by masking the load with the full indication.
  • Prevents extract when FIFO is empty, extract signal is ignored if FIFO is empty.
  • Almost full indication with parameter selectable depth for flow control.

Optional features

  • synchronous and asynchronous reset

Deliverables

  • verified RTL code
  • Access to detailed design documentation
  • 1 year support and customization service.

parameters table

parameters for memory based FIFO

Parameter

Valid values

description

WIDTH

 

FIFO width

DEPTH

any

FIFO depth

POINTER_WIDTH

Log(2) of DEPTH rounded up

Width of the memory address, depends on the memory depth

ALMOSTFULL_DEPTH

up to the FIFO address

the almost full depth is the number of available entries in the FIFO when the almostfull flow control signal is asserted. a value of 3 for example, means that there are 3 available entries before the FIFO gets full.

ALMOSTEMPTY_DEPTH

up to the FIFO address

the almost empty depth is the number of remaining entries in the FIFO when the almostempty flow control signal is asserted. a value of 3 for example, means that there are 3 remaining entries or less before the FIFO gets empty.

interface table

Signal name

Direction/width

description

clk

Input

Clock signal

resetb

Input

Active low reset signal, when asserted, pointers would return to zero and empty indication would be set

load

Input

Indicates the FIFO is to be written, will be ignored when FIFO is full and extract is de-asserted

extract

Input

Indicates a FIFO entry is to be read, will be ignored when FIFO is empty

empty

Output

Indication that the FIFO is empty. Extract operations are ignored while FIFO is empty

full

Output

Indication that the FIFO is full. Load operations are ignored while FIFO is full

datain

Input [WIDTH – 1:0]

Data input

dataout

Output [WIDTH – 1:0]

Data output

almostfull

output

the almostfull indication serves for flow control, it is asserted when the FIFO has ALMOSTFULL_DEPTH available entries or less

almostempty

output

the almostempty indication serves for flow control, it is asserted when the FIFO has ALMOSTEMPTY_DEPTH remaining entries or less. When set to 0 this signal would equal the empty signal.

FIFO functionality

Memory Based FIFO

The memory based synchronous pipeline FIFO is designed with an embedded  memory array and a set of read pointer and write pointer. the implementation is independent of the memory depth so a change to the memory size, often required in late design stages, would only require a change to the DEPTH or WIDTH parameters and a replacement of the memory instance.

The FIFO reset functionality is either synchronous or asynchronous; and should be selected according to the overall reset policy of the instantiating device.

The status indications are implemented using a counter.

When the FIFO is full, simultaneous load and extract is supported. This feature enables simple integration of the memory into a pipeline, allowing the FIFO to be viewed as a single sampling stage when empty.

The FIFO depth and width are parameters that can be set to any valid value at instantiation providing the embedded memory instance is selected accordingly.Additional parameter sets the width of the required address of the FIFO i.e., for a FIFO of depth 8 to 16 entries, 4 bits would be required.

Memory based FIFO should be used only for relatively large arrays where the area efficiency of the embedded memory results in a smaller and faster design.

Pipeline integration

The FIFO is designed to be inserted into a pipeline, so that if the FIFO is empty, it would act as a single pipeline sampling stage and will only be using the memory array if there are few entries accumulating in the FIFO.

this behavior is independent of the number of cycles it takes the memory to read an entry, making it useful at late floor-plan and timing stages where an additional sampling stage at the memory output is required for timing closure.

 

almost full FIFO flow control

The FIFO supports the almost full flow control functionality. It would assert the almostfull signal few cycles before the FIFO gets full, this will allow the flow to be stopped further up the pipe.

The FIFO would absorb the entries which are in flight so no data is lost. The ALMOSTFULL_DEPTH parameter should be set according to the number of sampling pipe stages between pipe stage the almostfull affect and the FIFO.

The disadvantage of the almostfull comes where the FIFO is read, the flow control would be de-asserted only after there are ALMOSTFULL_DEPTH free entries in the FIFO. to prevent bubbles at the FIFO output and FIFO under-runs, the FIFO depth should be at least double the size of the ALMOSTFULL_DEPTH so that it does not get empty before the new entries are loaded.

almost empty FIFO functionality

The FIFO that includes the almost empty flow control functionality would assert the almostempty signal some cycles before the FIFO gets empty, this will allow the flow to be stopped further down the pipe or can be used for other purposes like triggering upstream logic operation.

Load and extract functionality

Memory based FIFO

The load and extract operations of the FIFO impact the FIFO pointers and status counters.

When the load signal is asserted, the data on the datain is loaded into the position pointed by the write pointer and the pointer is then incremented by 1 to point to the next empty FIFO entry.

If the FIFO full indication is asserted, and the extract signal is not asserted, the load operation would be ignored and the pointer would not be incremented.

Simultaneous load and extract operations to the FIFO when full indication is asserted will result is a write of the datain to the FIFO and a read to the dataout. The full indication will remain asserted in that case.

Note that this functionality is to be used with caution as the upstream logic has to evaluate the extract signal to know if the current load value was actually loaded. To disable this feature, one can mask the load signal with the full indication at the FIFO inputs.

 

the below diagram shows the load and extract operations and the impact of them on the full and empty signals

memory FIFO load extract waveform

In the above drawing, at time T1, the empty signal is de-asserted after the first write operation is complete. At T2, simultaneous load and extract operations are performed when the FIFO is full. The result is that the FIFO remains full as data D5 is written into the FIFO and D1 is read, at the same time.

At time T3, the last written entry is extracted from the FIFO and the empty signal is asserted.

almost full FIFO

for the FIFO with almostfull indication, the load and extract operations are basically the same, the below diagram shows the behavior of  a 4 deep FIFO with an ALMOSTFULL_DEPTH set to 1 entry.

memory FIFO load extract with almost full waveform

Reset

The fifo_mem_asyncrst uses asynchronous active low reset signal. Once asserted, the pointers would return to their default value of 0 and the FIFO empty signal would be asserted.

The reset operation has no impact on the content of the memory array itself.

The fifo_mem_syncrst uses synchronous active low reset signal. Once asserted, the pointers would return to their default value of 0 at the rising edge of the clock and the FIFO empty signal would be asserted.

The reset operation has no impact on the content of the memory array itself.

Test Items

 

the below table summarizes the test items that were checked for the memory based FIFOs

some of the items are relevant only for specific examples.

 

Item name

Description

Reset functionality

Check reset assertion during operation, see that the pointers return to zero.

empty

Write to FIFO, check that FIFO empty indication is de-asserted.

Full functionality

Write to the FIFO the same number of entries as its depth, check that the full indication is asserted

Load when full

Load the FIFO when full indication is asserted, check that the loaded data is ignored and the FIFO ignores the load.

Simultaneous load and extract when full

Perform a simultaneous load and extract operations while the FIFO is full, see that both operations work, continue for multiple times, until written entry is read out.

bypass logic

perform extract and load operations when the FIFO is at the edge of being empty where bypass logic is effective, checking for ordering issues and bubbles.

simultaneous load and extract when almost empty

when there are only few entries in the FIFO, it will either use the memory or not, testing cases where it is sometimes using memory and sometimes not.

 

additional test items for almost full functionality

 

Item name

Description

Almost full assertion

Fill FIFO, see that the almostfull is asserted exactly ALMOSTFULL_DEPTH cycles before the full is asserted

almostfull de-assertion

Perform extract operation on a full FIFO, check that the almostfull is de-asserted after ALMOSTFULL_DEPTH entries are extracted.

 

Limitations

Simultaneous read and write while FIFO is full

For some embedded memory types a restriction on read and write to the same address on the same cycle exists. This FIFO implementation assumes that the memory allows for simultaneous write and read to the same address with no coherency issues. The case that would fail if this restriction exists is the case where there is a load and extract while the FIFO is full. To avoid this situation, mask the load signal with the full indication outside the FIFO.

Usability

The memory based FIFO is designed to be used within the context of a pipeline where its advantages are:

  1. Enable stalls in the pipeline, a FIFO allows the downstream logic to stop the pipe without losing data.
  2. Enables back pressure flow control to upstream logic with almostfull functionality so few pipe stages that cannot be stalled, can still continue to load data into the FIFO, stopping the pipeline at an earlier stage.
  3. The memory based pipeline FIFO can be added to a pipeline design without interrupting the pipeline functionality and when the FIFO is empty, it behaves as a single sampling stage.
  4. The option to use different memory read latency, enables sampling of the memory output, greatly improving the flexibility for floor-planning and timing closure

the FIFO can also be used for the following applications:

  1. where there is a need for a memory based FIFO that stores control logic along with the data and downstream logic requires to see the first entry outside the memory array. this type of application is usually related to queue systems and arbitrations.
  2. At block boundaries, a FIFO that can handle flow control for both upstream and downstream logic is simple to integrate and may serve to solve timing issues and enable safe sampling of the inter-block signals without logic impact.

Timing considerations

Data  in

When looking at the timing considerations for datain signal, one should look into the fanout of each data bit. The data bits actually reach the memory and the pipeline bypassing stages.

Data out

The timing for dataout in the memory based FIFO is coming directly from a flop, so no issues are expected.

Load and extract signals

The load and extract signal of the FIFO needs to reach all the control logic, pointers, counters and bypass control logic, those signal may be timing critical and should be considered.

Empty and full indications

The indications are calculated from the FIFO status counter, going only through simple comparators.

Application notes

Integrating into a pipeline

Integrating the memory based FIFO into a pipeline requires the connection of the full, empty, load and extract signals in the same way a simple FIFO would be connected.

The integration of the FIFO into a pipeline design requires the attention to flow control indications. The FIFO empty signal should be used for signaling downstream logic the there is available data at the FIFO outout. the full indication should be used for signaling the upstream logic to stall the pipe so data is not lost.