The Multiple FIFO component is a device which allows hosting multiple FIFO queues of the same depth within a single memory structure. Only one FIFO can be written and read in each clock cycle. Each load or extract request is qualified with the number of the FIFO to which it refers. Multiple FIFO control logic can be connected to a two port (1 write/1 read) memory structure with write latency of up to 4 cycles and read latency in range from 1 to 4 cycles. Status flags of FIFOs are designed to keep memory data coherence what is useful especially in case of different write and read latencies. Sharing common memory for multiple queues enables better power and area utilization and reduces overall resources used.
The below block diagram shows basic concept of multiple FIFO component:
- Parametrized FIFO number.
- Parametrized single FIFO width and depth.
- Full, empty and almost full status flags for each FIFO.
- Support for a wide range of memory read and write access latencies.
- Optional sampling stages on memory command and data interfaces.
- External memory interface, allowing simple integration to any memory model.
- Asynchronous or synchronous reset
- Verified RTL code
- Access to detailed design documentation
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