Ring oscillator performance monitor


This component contains verified RTL Verilog code for a process monitor counter designed to measure the frequency of a ring oscillator output for the purpose of correlating process voltage and temperature between devices and measuring on-chip variation (OCV). A ring oscillator is a device composed of an odd number of logical inverters whose output oscillates between the two logical levels. A frequency counter is used for measuring the ring oscillator rates. The measured signal is treated as asynchronous to the control clock and any clock frequency relation can be measured.

Block diagram

process monitor block diagram


  • Clock rate counting, for measuring the frequency of a clock.
  • Parameterized time counter width.
  • Parameterized frequency counter width.
  • Overflow indication.
  • Time counter period signal, enabling configuration for different frequencies.

Optional features

  • Synchronous and asynchronous reset

Product deliverables

  • Verified RTL code and simulation test-bench
  • Access to detailed design documentation
  • One year support and customization service.

parameters table


Valid values



even number > 50

The number of inverters on the oscillating ring. Should be sufficiently high to ensure low frequency.



Width of the frequency counter.



Width of the time counter.

Interface table

Signal name





Enable Ring oscillator and counters



Clock signal



Reset signal


Input [TIMEWIDTH-1:0]

Constant or configuration register value indicating the number of clocks for a predefined time period (typically one second)


Output [WIDTH-1:0]

Frequency counter result, updated each time the time counter expires.



Overflow indication, when this bit is set, the frequency counter value is not valid.


Ring Oscillator

A ring oscillator is a device composed of an odd number of logical inverters whose output oscillates between the two logical levels. The inverters are attached in a chain; the output of the last inverter is fed back into the first. Because a single inverter computes the logical NOT of its input, it can be shown that the last output of a chain of an odd number of inverters is the logical NOT of the first input. This final output is asserted a certain amount of time after the first input is asserted; the feedback of this last output to the input causes oscillation. The rate of the oscillation is a function of the delay of an inverter chain which is affected by the voltage, temperature and process (PVT) corner of the device. Using a large number of inverters, has an averaging effect, so any normal differences between the inverters are cancelled out and only the overall PVT affects the resulting oscillation rate.

The OCV of a device can be measured by instantiating multiple identical ring oscillators on different locations of the silicon die and comparing their resulting oscillation rate.

Ring Oscillator

Clock Frequency Counter

The frequency of oscillation is measured using a frequency counter. The implementation of the frequency counter is based on a time counter running in the control clock domain and a second counter running at the oscillator clock. The period of the time counter is typically set to 1 second so the number of clock cycles counted in the measurement counter during this period is actually the frequency of the oscillation clock.


The ring oscillator, one enabled, starts to toggle at a rate correlating to the process, voltage and temperature case. The frequency counter performs the measurement of the rate of the ring oscillator output. The frequency counter has two counters, one for measuring a predefined time period using the main control clock, and the other for measuring the number of clocks occurring during that time, running in the measured clock. In case the time counter, counts a period of 1 second, the resulting frequency counter, is actually the rate of measured clock.

Selecting the ring oscillator length

The number of inverters in the ring oscillator should allow for the fast corner case to reach frequencies as low as 50Mhz, keeping it well below control clock frequency.

Overflow case

The overflow signal serves as an indication that the frequency counter has overrun. Typically, in order to reduce the amount of logic used for the frequency counter, the number of bits used is low, accommodating the expected number of clocks during the time period. For example, for measuring a slow clock, the expected result is low, so a smaller counter is enough and in case the clock is faster, an overflow indication would be sufficient to signal that the frequency cannot be measured for this time period.


The design can be reset either synchronously or asynchronously, depending on the overall reset policy of the instantiating design.

Test Items

the below table summarizes the test items that were checked

Item name


Ring oscillator rate

Measure with different inverter delay. Use, jittering delays to induce multiple different measurements.

Counter size

Change event counter size to produce overflow.


Check overflow event is set only for the correct cases.


Selecting width parameters

Setting the correct width for the counters is essential for proper operation. The time counter should be able to accommodate a 1 second delay, so for example, at 250Mhz, the counter should be set to 1,000,000,000/4 = ‘hEE6B280 so for this frequency of control clock you would need 28 bits at least. Note that measuring with higher number of bits may be more accurate and result in fewer variations between consecutive measurements.

For the frequency counter to function properly and enable measurement of the intended oscillator output frequency, care should be taken for the following cases:




Measured frequency higher than control frequency

Set the WIDTH parameter to be higher that the TIMEWIDTH, allowing for the maximal frequency ratio.

Measured frequency lower than control frequency

Set the WIDTH parameter to be lower that the TIMEWIDTH, allowing for the maximal frequency ratio.