• clock Deskew DLL

    The RTLery Deskew DLL core implement a fully digital delay-line based DLL structure that effectively eliminates the skew between two identical frequency clock signals. The Delay-Locked Loop (DLL) provides an on-chip digital deskew circuit that effectively generates clock output signals with a net zero delay between them. The DLL can be used for eliminating the delay of a clock insertion delay effectively eliminating delay from the external clock input pin to the clock tree loads within the device.

  • Clock frequency divider

    Clock frequency dividers generate slower clocks from a faster reference. Typically additional clock division is required for applications requiring very slow clocks, such as video and voice processing devices or the case where fine granularity of division is required. Such a clock divider would typically be placed after the device PLL.

  • DDRx DLL

    The DDR DLL core implements a master-slave structure where a master measures the cycle time and one or more slaves are used for delaying signals such as DDR DQS strobe.

  • PSRAM memory controller

    The PSRAM memory controller supports the main PSRAM standard for most memory access modes including configuration cycles, asynchronous access and synchronous accesses. The different modes are supported separately and the operation mode is be pre-selected through the controller configuration interface.