Clock deskew dll


The RTLery Deskew DLL core implement a fully digital delay-line based DLL structure that effectively eliminates the skew between two identical frequency clock signals. The Delay-Locked Loop (DLL) provides an on-chip digital deskew circuit that effectively generates clock output signals with a net zero delay between them. The DLL can be used for eliminating the delay of a clock insertion delay effectively eliminating delay from the external clock input pin to the clock tree loads within the device.

The DLL maintains the skew between its Feedback input and the reference clock input below a NAND cells delay independent of PVT conditions. The core is using digital standard-cell based delay lines with granularity of 1 standard minimal NAND cells in any selected library or process corner and does not add duty cycle distortions or significant jitter to the clock signal.

The DLL provides glitch free clock output both during lock time and during normal operation. If a specific pre-defined skew is required, the DLL can effectively push forward or back the output clock, using small delay lines on the reference and feedback clocks. Adding few taps to the reference delay will effectively push the clock forward while adding few taps on the feedback clock will effectively push the clock backward. This feature allows for fine tuning of the output clock edge location for phase sensitive applications.

The DLL core also provide means for overriding the main delay line to any specific value, either for characterization purposes or any other need, effectively overriding the automatic compensation mechanism in that case.

The core is structured from delay line taps which are pre-designed and pre-placed separately and are suited for minimal granularity, and additional control is implemented using synthesizable logic, providing initialization and locking control functionality. The hardened predesigned macros contain only standard cells, making portability between process nodes and different foundries fairly straight forward, with limited timing closure complexity. The DLL design has low cell count of approximately 4k cells.

Block diagrams

Deskew DLL block diagram

Using the Deskew DLL to eliminate clock insertion delay:

Deskew DLL integration for clock skew elimination


  • PVT compensation – tracking reference clock edge under any PVT condition, compensating temperature and voltage changes during operation.
  • Option for offsetting or overwriting the delay for testability purpose or for optimizing the output clock edge placement.
  • Structure - The DLL uses only standard library cells and does not require additional analog voltage supplies.
  • Jitter and errors - The DLL tap delay granularity error is limited to a NAND cell delay (30-70ps at 40G).
  • Frequency range - The DLL supports input clock of frequencies between 300Mhz and 700Mhz using a 128 tap configuration.
  • Adoptable for larger tap count (32, 64, 128, 256, 512) and any process node.
  • Glitch free delay update, allows constant tracking during normal operation with no impact to downstream logic.
  •  Initialization - The DLL is started once the clocks are stable. The initialization sequence locks the DLL to match the feedback clock to the input clock. A signal indicates that the DLL is locked.
  • Testability - The Deskew DLL includes full scan support for ATPG testability.


  • Netlist for delay lines and sensitive logic
  • RTL for control and initialization logic                                                                                              
  • Complete P&R instruction details to be used by physical design engineer
  • Complete timing closure instructions
  • DFT & testing instructions
  • Complete documentation, user guide and design specifications
  • Timing and P&R review


The function of the Deskew DLL is to effectively cancel out the insertion delay between the root of a clock tree and its leaf pins, aligning the edges of the two clocks. The DLL delay line is used for delaying the output clock to the point where it is aligned to the reference clock edge. The DLL control logic would track the relation between the clocks and increase or decrease the delay line tap count constantly, keeping the edges closely aligned. The control logic is only shifted by one tap at a time and measures the relation between the edges over many clock cycle, preventing overshoots and false changes.

Deskew DLL waveform of function

Clocking structure

The DLL functions with 2 operating clocks in addition to the delayed clock. The cfg_clk is actually the clock of the system control logic, and is used for sampling the control information delivered by the system. Using the actual system clock serves to provide a clean timing of the DLL interface to the system.

The cclk is the control clock used for operating the DLL control logic and state-machines. The clock is limited to either same frequency or slower than the reference clock input with no specific relation between the two clocks. The cclk enables the usage of slower frequency for operating the DLL where the reference clock frequency may be much higher. Typically, the cclk may be as slow as the cfg_clk or may be fixed at half the reference clock frequency in other cases.

The DLL uses full bidirectional synchronization between the cfg_clk and the cclk, ensuring any configuration is used correctly.

Initialization and locking

  1. The sequence of initialization of the DLL is listed in the following list:
  2. The input reference clock and feedback clocks are stable at the required frequency.
  3. DLL is enabled by setting config_dll_enable = 1
  4. Wait for  config_dll_deskew_locked to be asserted, check that config_dll_deskew_overflow is negated
  5. Continue normal operation

Offset and override options

The DLL supports the option to offset the resulting output clock either forward or backward in relation to the reference clock using a 32 tap delay line for each direction. Allowing an offset may support fine tuning of the actual relation between the clocks for optimal edge allocation. The edge shifting is done by delaying either the reference clock edge or the feedback clock edge used for edge comparison. When shifting the reference clock edge forward before comparing it to the feedback clock, the resulting feedback clock is shifted forward in relation to the original reference clock. When delaying the feedback clock before comparing it to the reference clock, the resulting feedback clock is shifted backward in relation to the original reference clock. The offset is measured in single NAND cell units.

The option to override the delay line tap count may be used for calibration purposes of for setting a fixed offset between the clocks.

In addition to offsetting and overriding the DLL delay line, the delay line automatic tracking of the reference clock edge may be disabled at any point in time.

For all those debug features, the delay line would take 20-50 cclk cycles to stabilize on the required setting.

Calculating supported frequency

The maximal supported frequency is calculated by considering the delay of a NAND cell, assuming a minimum of 16 taps. The calculation should take into account the insertion delay (the delay from the output of the DLL to the feedback input and some intrinsic delay of the delay line not accounted for in taps. By adding all those delays, the minimal clock cycle time safely trackable by the DLL may be calculated. A typical frequency assuming a NAND delay of 30ps and an insertion delay of 1ns would be 500-600Mhz.

The minimal frequency is calculated based on the length of the delay line, and assuming a fast process.

DFT and testability

The DLL supports scan ATPG for ATE fault detection. The scan chains of the hardened non-synthesizable parts of the DLL are pre-inserted into the netlist and cover most sequential and most combinational elements of the hardened design. For the synthesizable control logic, scan can be inserted using the normal DFT flow of the surrounding logic.

Deskew DLL Interface table

Signal name





reference clock input of the DLL



Control clock, this is typically a slower clock used for the DLL control logic. There is no alignment requirement between the cclk and the inclk or cfg_clk.



Asynchronous reset signal used for cclk clock domain



configiration clock input, used for controlling the configuration busses of the DLL, this clock should be used for driving control signals to the DLL



Asynchronous reset signal used for cfg_clk clock domain


Input [4:0]

Feedback offset value, used for delaying the feedback clock to the DLL by up to 31 taps.


Input [4:0]

Reference clock offset value, used for delaying the reference clock to the DLL by up to 31 taps.


Input [7:0]

DLL delay line override value, may be used for overriding the delay line tap count.



Enable DLL delay line override.



Disable DLL tracking, causes the DLL delay line to remain at the last tap count and not respond to PVT changes



DLL software reset, allows to reset the DLL and return it to the original state before initialization.






DLL enable signal, starts the DLL locking operation. This signal should be asserted after the input clocks are stable at the required frequency. The signal is to be kept asserted while the master is active. 



DLL lock indication, indicates that the DLL is locked to the reference clock frequency and the output can be used.


Output [7:0]

DLL tap measurement, to be used as information about the current delay line tap count



Delay line overflow, indicates that the tracking frequency is too low to be tracked. In this case the delay would remain at the maximal value.



Scan enable signal, select shift operation for sequential elements.



Puts the master into scan mode



Scan chain input for hardened part



Scan chain output for hardened part


Test Items

The following test item list summarizes the tests that were executed on the DLL. Some of the tests are also available as part of the environment deliverables.

All tests would run multiple times with different simulation seeds.


Item name



Simple locking cycle

Check that the DLL is locked using the typical lock sequence


Check DLL under overflow condition

Check that overflow signal is asserted, verify the delay line is kept at the maximal value.


Manual offset

Check offset in both directions using the reference and feedback delay lines, verify that the tested clock edges are shifted one against the other correctly, check DLL returns to normal locking when offset removed


Manual override

Check manual offset option, check that the DLL changes gradually to the required tap count, check DLL returns to normal tracking when override is disabled


Disable update

Check that the DLL remains fixed when updates are disabled. Check normal operation is resumed whem disable is removed.


Minimal frequency

Check for minimal frequency using fast process delay line elements delay. Check frequency out of the range; verify DLL locks for a maximal delay of the delay line.


Maximal frequency

Check for maximal frequency using slow process; verify DLL lock with minimal delay.