Clock frequency divider


Clock frequency dividers generate slower clocks from a faster reference. Typically additional clock division is required for applications requiring very slow clocks, such as video and voice processing devices or the case where fine granularity of division is required. Such a clock divider would typically be placed after the device PLL. This clock divider component implements a clock frequency synthesizer or divider which is capable of dividing a clock with a granularity of ½ cycles and can be used for generating a clock at almost any ratio within it maximal range. The component synthesizes a clock waveform according to the defined configuration. The component implementation includes a hardened block which contains the divider core and a synthesizable control logic part. To enable simple and smooth implementation and integration, the component documentation includes detailed physical design instruction and signoff checks.

Block diagram



clock frequency divider block disagram

  • Divide by any ratio within the divider maximal divide ratio
  • 50% duty cycle for both even and odd division ratios
  • Capability to generate any clock waveform required
  • Glitch free divide parameters change for clean on-the-fly frequency change.
  • Slow control interface clock for improved timing

  • Low gate count and high frequency support
  • Bypass functionality


  • Verified RTL code and netlist for divider core.
  • Access to detailed design documentation
  • Detailed physical design instructions for divcore block
  • Review for layout and STA scripts
  • Optional full physical design implementation of the hardened clock divcore macro or the whole design.
  • 1 year support and optional customization service.


parameters table


Valid values




Maximal clock division ratio, controls the width of the division logic. Up to 32.


Interface table

Signal name





Divider bypass, this is an asynchronous bypass, serving to bypass the divider entirely.



Divider enable, used for enabling the divide operation and for frequency change.


Input [2*MAXRATIO-1:0]

Configuration vector for the divider, each bit represents a ½ cycle.


Input [log(MAXRATIO) -1:0]

Length of the divider period, represents the number of clocks the divider would go through in each period.



Input clock



Control clock, used for clocking the divider control logic, all control inputs are related to this clock.



Asynchronous reset signal, serving both clock domains.



Output  divided or bypassed clock


The clock divider is capable of dividing a clock to the granularity of half a cycle. Consequently it can divide the clock to any wave form as described in the configuration vector and use any period within the number of cycles in the divider length. For example, a MAXRATIO=32 divider is a 64 elements long divider, the divider period length may be any number from 2 to 32. The maximal division ratio of the divider is 1/32.

Control clocking

The divider can use high frequency input clocks as the control signal and most of the control logic is performed at a lower frequency ctrlclk. The ctrlclk frequency should be at least 4 times slower than the inclk. For dividing PLL output, it is best to use the PLL reference clock as a control clock for the divider. The divider control logic synchronizes the information to the inclk domain and therefore, some minimal time should be allowed between consecutive configuration changes.

Divider Configuration

The clock divider has 2 configurations to set; the first is the period of operation selected by the divider length. For a period of 15 cycles, configure the decimal 15 to the divlength field in the configuration register.

The divider configuration vector is the actual waveform required for the clock within the divider period. The waveform is to be configured as demonstrated in the below drawing:

divider configuration example


In the above example, the divider is used for dividing a clock by 3.5 using an uneven duty-cycle. The divider is configured to 7 clocks as the number of clocks must be an integer number. Within the 7 clocks, the divider_config vector is used for specifying the waveform of the required clock output where each bit corresponds to a ½ cycles or phase of the input clock. The rest of the bits in the divider_config vector must be configured to zero values.

Using another example to demonstrate the capabilities of the divider shows it can be used to divide the clock by 14/17. Configuring the divlength to 17 and the div_config vector to the below waveform will result in the required frequency division. Naturally the clock is not of 50% duty cycle and the logic clocked by such a clock waveform should meet the higher frequency timing requirements, but for many applications such a clock is sufficient for proper operation.


Divider initialization

The initialization sequence of the divider includes the following steps:

1.    Check that both the ctrlclk and inclk are running.

2.    De-assert rstn signal to get the divider out of reset.

3.    Program the divlength and divider_config according to the required frequency.

4.   Wait 32 ctrlclk cycles

5.    Assert divenable signal, enabling the divider.

Divider bypass

The functionality of the divider bypass enables a bypass of the divider, either for testability of for other requirements. The bypassing entry and exit sequence is not designed as a glitch free operation and it is advisable to use it only for static situations where the divider is not used.

Divider frequency change

The clock divider is capable of changing either the divlength or the divider_config or both without glitches if the following sequence is followed:

1.    De-assert divenable. The result would be that the clock is turned off with no glitches.

2.    Change the divlength and divider_config according to the required frequency.

3.    Wait at least 32 ctrlclk cycles 

4.    Assert divenable signal, enabling the divider.

There are no specific time delay requirement between the operations but is would take the divider up to 2*MAXRATIO cycles to complete the frequency change in a clean and glitch free manner.

Implementation options

The clock divider requires that the clock divcore part (see block diagram above) would be physically implemented manually, allowing for better optimization of the divider timing and P&R. the implementation section of this documentation includes detailed physical design instructions, allowing every physical designer to perform place and route, as well as static timing for this hardened block. 

Test Items

Item name


Configuration options

Check different configuration options, verify frequency and waveform is according to the configured values.

Frequency change sequence

Check frequency change sequence; see no glitches on output clock. Check different sequence delay between the different configurations registers change.

Divider bypass

Check bypass functionality


Setting the parameter

The MAXRATIO parameter is to be set to the maximal required clock frequency ratio. The parameter is limited to 32 due to implementation restrictions and values above 32 should not be used. A MAXRATIO of 32 means that the maximal frequency ratio required is 1/32 where the divided clock is 32 times slower than the input clock.

Divider integration diagram

A clock divider of this type is typically integrated into a device top level design right at the output of a PLL and is used for generating clocks for slower clock functionalities. The divider enables on-the-fly frequency change following a simple change sequence. This functionality simplifies debug and validation of the device.

clock divider integration


The typical integration of the clock divider into a top level design is shown in the above drawing.

Physical integration

At the physical integration stage, the divider should be placed at the top level PLL vecinity, close to the reference clock input. The divclk output would become the clock source of the device core logic.