Psram memory controller

 
 
SiliconProven

The PSRAM memory controller supports the main PSRAM standard for most memory access modes including configuration cycles, asynchronous access and synchronous accesses. The different modes are supported separately and the operation mode is be pre-selected through the controller configuration interface.

The controller enables smooth integration of a PSRAM memory into devices targeted for mobile applications. The controller supports major PSRAM memory vendors and was tested with simulation models supplied by them.

The PSRAM memory controller implementation is designed to give the user full flexibility for driving the memory control signal and the option to choose the correct data driving and sampling point for timing adjustment. Flexible signal timing enables the system designer to overcome timing issues and configure the controller to optimal timing.

The controller supports burst accesses of multiple memory entries, as well as the PSRAM predefined address wrap burst mode. It has the capability to drive configuration cycles to the memory both is software access mode and using the CRE signal by using a dedicated interface for the application to drive configuration cycles to the PSRAM memory.

The controller uses an internal clock which is 2-4 times faster than the external required clock, enabling multiple timing options for accessing the external memory

Block diagram

PSRAM memory controller block diagram

 

Features

  • 16bit data word size, 21 bits address using address and data multiplexing
  • Synchronous, Asynchronous and configuration modes of operation  
  • Flexible and programmable control signals timing
  • Fixed latency, Variable latency, WAIT functionality
  • Burst and continues modes of addressing.
  • Back to back transactions for maximal bandwidth
  • Pipelined application interface handshake.
  • robust data sampling logic with multiple sampling options
  • use of faster controller clock with internal clock divider for generating output clock
  • controller disable mode with graceful shutdown
  • support for software and CRE based configuration transactions through external interface

Deliverables

  • Verified RTL code.
  • Access to detailed documentation and datasheet
  • One year support and customization service

Operation modes

The PSRAM controller supports 4 operation modes of the memory. For functional access, it supports both Asynchronous mode and the burst synchronous mode.

Memory configuration cycles are used for writing and reading the memory configuration registers (RCR, DIDR, BCR). The controller supports both modes available from the memory, it can be used to sequence the software configuration access or the CRE based configuration cycle. All access to memory configuration registers requires the use of the controller dedicated configuration cycles interface and modification of the timing parameters to suit the memory transaction requirements.

 

Mode

Encoding

description

Software Configuration cycles mode

2’b10

The controller is configured for configuration mode accesses. The transactions to the memory are sourced from the controller register interface using software access transactions.

CRE Configuration cycles mode

2’b11

The controller is configured for configuration mode accesses. The transactions to the memory are sourced from the controller register interface using software access transactions.

Synchronous burst mode

2’b00

Synchronous fixed or variable latency burst mode. Supports continued and wrap bursts.

Asynchronous mode

2’b01

Asynchronous PSRAM access mode. The controller is configured with the timing parameters for asynchronous mode and clock output is disabled.

Asynchronous mode

The PSRAM controller supports the memory Asynchronous mode. Asynchronous mode uses industry-standard SRAM control signals ( CE#, ADV#, OE#, WE#). An asynchronous transaction example is shown in the following figure:

PSRAM Asynchronous read

The controller supports the asynchronous transaction through the configuration of the timing per each of the interface signals. The setting of the timing control parameters allows the user to control every memory interface signal separately, as well as the controller data sampling point and data driving point with a granularity of one internal controller clock cycle.

Each control signal has two parameters, one for its assertion time and the second for its de-assertion time. The time is measured from the first edge of each transaction.

Synchronous burst access mode

The PSRAM memory can be accessed in synchronous burst. The burst may be of pre-defined length, supporting burst wrap addressing or continues. The controller supports both bust mode and continues mode where the length of the burst is supplied by the application interface. The controller splits the transaction if necessary, in order to meet memory maximal CE# assertion time and page boundary crossing. The controller would not cross page boundary and will split a transaction accordingly. The following example shows a synchronous write burst access:

PSRAM write transaction timing

The controller supports burst accesses memory signals timing through the timing parameters, enabling the user to configure the assertion and de-assertion time of each of the control signals and the internal signals controlling the drive and sample of the memory interface signals.

Software configuration cycles

The PSRAM requires configuration cycles for the purpose of changing mode and operation parameters. The PSRAM controller supports configuration cycles as part of the normal transaction interface to the application.

To send a software configuration transaction to the memory, the controller timing parameters should be programmed with the required timing parameters for asynchronous access and the software configuration mode of the controller should be enabled.

The sequence of read and write accesses required to issue a memory configuration register write or read is then sequenced through a dedicated interface of the controller. Connecting this interface to CPU or software controlled registers of the application logic, will enable the user to perform the sequence from the software.

Configuration Access Using CRE

The memory control registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (CRE) input is HIGH.

When the controller is set into “CRE Configuration cycles mode” it will generate access to the memory configuration register for each transaction issued through the controller dedicated configuration cycle interface.

Application command and data interface

The controller application interface supports a FIFO handshake interface, where the transaction from the application is outstanding until it is acknowledged by the controller, allowing the application to move to the next transaction.

FIFO handshake interface

The FIFO Handshake interface is well suited for connecting the controller to a FIFO of requests using a fall-through FIFO and connecting the command signal to the FIFO valid ( not empty) indication and the address and command attributes to the FIFO data. The cmd_ack signal would be connected to the FIFO read (extract) signal.

The application write data interface supports a FIFO handshake interface – where the data from the application is outstanding until it is acknowledged by the controller, allowing the application to move to the next data of the burst. The data is acknowledge at the time it is required to be sent on the bus so there is a single sampling stage of the data within the controller.

data write handshake

The FIFO handshake requires the application to have the data ready for sending and will send acknowledge for each data which is consumed and sent on the external bus.

The FIFO handshake can directly connect to a data FIFO where the data_valid is connected to the FIFO valid signal (not empty indication) and the wr_data_ack is to be connected to the FIFO read (extract signal).

Application read data interface

The read data interface from the controller to the application contains a rd_data signal and a rd_valid signal. For each transaction, the controller would assert the rd_valid and drive the rd_data according to the number of read data in the transaction, as indicated by the transaction size.

read data application interface

The data returned to the application is transferred from the memory in the same order it returns from the memory, so if the memory is configured for burst wrapping mode, the application must be ready to accept the data according to the PSRAM specification order.

Addressing and transaction splitting

The controller supports a direct mapping of address from the application interface to the memory. The address of sequential bursts would be driven to the memory as it is received.

For burst wrap mode, given the size of the transaction fits the burst size configured in the memory control registers, the controller would drive the burst address as it is received from the application interface.

 

Memory configuration

Transaction Size limitation

Sequential burst

MAX_TRANS_SIZE

Wrap burst

Configured Burst size

Continues burst

MAX_TRANS_SIZE

The burst order would be dependent only on the memory BCR configuration.

For burst-wrap mode, where the configuration bit config_brust_wrap_mode is set, the controller splits the transaction according to the config_burst_size configuration signal. An unaligned transaction with a size which is longer than the burst_size would be split into accesses with the same offset from the burst start.

The controller splits the incoming transaction according to their initial address and size. Each part of the split transaction would appear on the memory bus as a separate continues or burst transaction. The application would receive the number of words as indicated by the transaction size.

The controller uses few rules for splitting transactions:

rule

description

TCEM length

Stop the transaction on a tCEM limitation for maximal CE# assertion time. This will prevent violation of the memory tCEM delay limitation.

Page size

Stop the transaction on page boundary. This will prevent page boundary crossing. A new memory access would begin at the first address of the new page. The same method is used in both fixed and variable latency (WAIT) modes.

Asynchronous mode

In Asynchronous mode, the transaction would be split into single access transactions where each data word is accessed separately.

Burst wrap mode

The transaction is split into config_burst_size bursts to memory. Address for all split bursts will have the same offset from the burst size aligned address.

 

Interface description

The following parameters can be set for controller instantiation

Parameter

Valid values

description

MAX_TRANS_SIZE

63-memory size

Sets the maximal transaction size for application interface transactions

PARM_BITS

5-8

Number of bits to be used for timing parameter, this is a function of the internal clock divide ratio and the length of the transaction.

 

 

 

 

Signal name

width

Direction

description

Clocking and reset

 

 

 

clk

1

Input

Clock. The clock is required to be stable and toggling before the controller is enabled

reset_n

1

Input

Asynchronous reset (active low). reset all flops in the design

Application command and data interface signals

 

 

 

wr_cmd

1

Input

Write Burst command

rd_cmd

1

Input

Read Burst command

addr

21

Input

Address of Write or Read. The actual address of the memory is dependent on the burst size of the memory access as all accesses are aligned to the burst size.

size

21

Input

Transaction size. For burst access, this signal should be kept constant at the required burst length. Transaction size can be any length.

wr_data_ack

1

Output

The controller accepted the write data. The signal would be asserted for each data chunk of the command. The controller assumes data is available (wr_valid asserted)  when request asserted

wr_valid

1

Input

Write valid indication, signaling that data is available for a write transaction. The controller assumes all data in ready before a write transaction starts.

wr_data

16

Input

Write Data (word by word)

rd_valid

1

Output

Read valid strobe – to use as sample enable for rd_data.

One cycle pulse for each data word.

rd_data

16

Output

Read Data (Word by word)

cmd_ack

1

Output

Command accepted by the controller, the next command may be issued.

Application timing configuration interface signals

 

 

 

Configuration for memory signals

 

 

 

config_mem_CSB_assert_time

5

Input

CS# assert time

config_mem_CSB_deassert_time

5

Input

CS# de-assert time

config_mem_ADVB_assert_time

5

Input

ADV# assert time

config_mem_ADVB_deassert_time

5

Input

ADV# de-assert time

config_mem_WEB_assert_time

5

Input

WE# assert time

config_mem_WEB_deassert_time

5

Input

WE# de-assert time

config_mem_OEB_assert_time

5

Input

OE# assert time

config_mem_OEB_deassert_time

5

Input

OE# de-assert time

Configuration for controller signals

 

 

 

config_addr_drive_assert_time

5

Input

Address drive time. The address will be drive until the mem_ADVB is de-asserted indicating the address phase is complete.

config_read_data_samp_negedge

1

Input

Enable sampling of read data on the falling edge of clock.

config_read_data_samp_return

1

Input

Enable sampling of the read data with the returning external clock psrm_clk_in, when active, the config_read_data_samp_negedge setting is used for selecting posedge or negedge of the psrm_clk_in.

config_read_data_start_time

5

Input

Indicates the start time of the read data phase, all subsequent burst read data are sampled with external clock spaces from the burst start time.

config_write_data_start_time

5

Input

Indicates the start time of the write data phase, all subsequent burst write data are driven with external clock spaces from the burst start time.

config_last_data_cycle_assert_time

5

Input

Indicates the time where the last data cycle of the transaction starts. This will be used for starting back-to-back transactions

config_last_rd_trans_cycle_assert_time

5

Input

Indicates the last cycle of the read transaction where all control signals should be returned to inactive value

config_last_wr_trans_cycle_assert_time

5

Input

Indicates the last cycle of the write transaction where all control signals should be returned to inactive value

config_tcem_cycle_count

12

Input

sets the number of cycles the TCEM would count between times CE is de-asserted if a CE is de-asserted this timeout counter is reset and starts again, one expired it will force CE de-assertion at the end of the current transaction

Mode configuration

 

 

 

config_page_size

12

Input

Memory page size. Supports memory page sizes of 256, 1024 and 2048. Typically PSRAM page size is 256.

config_pswait_delay_enable

1

Input

Indicates that the PSRAM uses the early WAIT signaling option. This should be set in conjunction with the PSRAM WAIT configuration bits.

config_pswait_polarity

1

Input

Indicates that the PSRAM active low WAIT signal polarity. This should be set in conjunction with the PSRAM WAIT configuration bits.

1 – using active low WAIT

0 – using active high WAIT

config_pswait_use

1

Input

Indicates that the PSRAM is using WAIT and is in variable latency mode. This should be set in conjunction with the PSRAM WAIT configuration bits

config_mode

2

Input

2’b00 : synchronous mode

2’b01 : Asynchronous mode

2’b10 : software configuration access.

2’b11 : CRE configuration access.

config_clk_out_en

1

Input

Enable clock output, determines if the controller drives the external psrm_clk signal

config_enable

1

Input

Controller enable, if set to 0, all memory and application interface signals will be inactive and the controller will not drive or accept transactions.

config_clk_div

3

Input

Clock divider configuration, supported values 2, 3 and 4.

config_output_clk_use_fall_edge

1

Input

Enable improved hold time for control signal by driving the clock signal half clk earlier.

config_brust_wrap_mode

1

Input

Sets the controller into wrap burst mode. The setting of this bit should match the memory configuration register setting.

  1. Wrap burst mode
  1. Continues or sequential burst mode

config_brust_size

6

Input

Indicates the size of the burst, this setting should match the memory configuration register. Supported values are 4,8,16,32

Configuration change

 

 

 

config_valid

1

Input

Indicates that the configuration signals are valid. This signal enables configuration change so when changing the timing configuration signals this signals is set to 0 so the newly set timing do not affect the controller behavior. Once set to 1 the configuration is used by the controller.

Configuration cycle control

 

 

 

cfgcyc_rdnwr 

1

Input

selects between read and write configuration cycles and is qualified with cfgcyc_rdwr_enable that triggers the configuration command

cfgcyc_wr_reg_val

16

Input

Configuration data to be written into configuration register.

cfgcyc_rdwr_enable

1

Input

Enable the configuration cycle. The controller should be in configuration cycle mode. The enable is to be reset to 0 and re-asserted to 1 for each register access.

cfgcyc_rd_reg_val

16

Output

Configuration register read data.

cfgcyc_ready

1

Output

Configuration cycles interface is ready for the next transaction.

cfgcyc_cre_mode_reg_sel

2

Input

CRE configuration cycles register selection:

  1. Select RCR
  2. Select DIDR
  1. Select BCR

 

Verification environment

The verification environment used for verifying the PSRAM controller consists of the following:

  1. A generator of transactions, generating reads and writes with random data
  2. Self-checking mechanism for memory reads and writes, using a sparse memory and backdoor access to the PSRAM memory.
  3. Configuration interface BFM
  4. Predefined sequences for configuring timing parameters and modes for the common operating conditions.
  5. Test tasks for generating test sequences of interest.
  6. End-of-test compare for comparing sparse memory to the actual PSRAM device model.

Verification method

The verification of the PSRAM memory controller is based on a self-checking memory read and write transactions and detailed testing of the controller features and corner case scenarios according to a pre-defined test plan.

The tests cover the different cases through direct sequencing of the different scenarios. Data is generated randomly and checked on the end of every transaction. In most tests the addresses are randomized within the available range.

When testing different operation parameters, the tests cover all options of the specific parameter and any related parameters are covered in the same test.

The tests for PSRAM configuration cycles include all the sequences for changing a timing parameter on the controller, as well as re-programming the operation modes of the PSRAM itself.  

All the dedicated test items defined on the test plan below were implemented and checked both manually and through the data self-checking mechanism. 

Test items

The following table contains the test items checked for the PSRAM controller. The tests are directed to the specific test scenario described. Additional random tests are run separately.

 

#

Item name

Description

1

Software configuration

  • Perform multiple software configuration access sequences for read and write of the configuration registers.
  • Simulate controller bring-up in real application scenario. Verify configuration interface of the controller

2

Operation modes

  • Change operation modes between synchronous and asynchronous and perform read and write transactions in each.
  • Change operation mode during transactions, check graceful replacement of mode.
  • Combine PSRAM configuration cycles during asynchronous and synchronous mode.

3

Back to back write

-          Back to back write transaction with increasing distance, check for continues CE#

-          Random and consecutive address

-          Different burst length

4

Back to back read

-          Back to back read with increasing distance, check for CE# de-asserted between transactions

-          Random and consecutive addresses

-          Different burst lengths

5

Back to back random type transactions

-          Random type, alternating read and write

-          Check for read to write CE# disabled

-          Check for write-to-read back to back

 

TCEM

-          Check TCEM functionality and configuration count.

-          Enlarge counter and see memory model failure

-          Check for 1 cycle CE# de-asserted when expired.

7

Configuration mode

-          Enter configuration mode during a read/write

-          Check for transaction complete and idle

-          Check normal transaction stopped during configuration mode

-          Check transaction re-start after configuration mode exit

-          Check transition from Synchronous and Asynchronous mode

8

Configuration cycles

-          Check multiple configuration cycles, reads and writes

-          Check configuration register interface handshake

-          Check returned data consistent with register values

-           

9

Timing parameters

-          Check each parameter in all the possible locations and pulse widths

-          Run through loops for setting, verify through sampling of the sequence counter on assert and de-assert.

-          Check timing parameters for de-assertion during next transaction

10

Sampling logic

-          Sample using all modes

-          External clock sampling

-          Negedge and posedge sampling

11

Data drive logic

-          Drive data on all possible locations

-          Check application handshake interface signals for data driving

-           

12

Transaction termination

-          Set last_data_cycle to different locations in relation to transaction_last_cycle, check for proper back to back and separate transactions.

13

Hold optimization

-          Enable hold optimization and check clock is driven ½ a cycle before.

-          Check disabled mode

14

Application interface

-          Check application interface in Cmd-ready mode

-          Check in req-ack mode.

15

Divide by 2

-          Run some of the tests in the divide by 2 configuration

16

Generic testing

-          Perform a mix of transactions for common operation modes

 

Graceful disable

-          Disable the controller using the config_enable signal.

-          Check controller stops where memory is in IDLE

17

Asynchronous mode

-          Multiple asynchronous transactions

18

Latency 3

-          Set the PSRAM to latency 3

-          Run mix of reads and writes

 

 

Application interfacing

The controller command and data interfaces are to be connected to the application using one of the two operation modes described in Application command interfacesection.

The configuration signals should be connected to software controlled registers so the software would be able to set the controller into the required mode and timing parameters.

I/O connectivity

Most of the controller signals are output only signal and the related I/O should be set to operate as an output during the controller operation.

The psrm_Adq signals are bidirectional to allow for both read and write data as well as the transaction address to use the same bus.

The controller controls the output enable of the psrm_Adq bus and drives the active high psrm_adq_oe signal. The timing of the signal is controlled by timing parameter, allowing for flexibility in bus drive control for proper timing and bus contention control