Frequently asked questions

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The RTLery website provides RTL design engineers with verified and well documented code examples for many of the generic components used in different designs across the semiconductor industry.

The site contains a large variety of components from the simple FIFO to the most complicated arbitration algorithms and functions.

The goal of RTLery is to make knowledge accumulation faster and enable the designer to concentrate on the design architectural challenges and reach his target functionality faster. Using pre-verified generic components will save debugging time and reduce overall design and verification effort.

Registration to the site is simple,  just go to the "Create new account" above the login form , fill in some information, accept the site terms and you can start using the site.

The RTLery site is open to all qualified RTL design and verification engineers working for fabless companies, design and verification service providers, EDA companies and chipmakers as well as individual freelancers. The preferred way to register would be using a corporate email address . RTLery site is not targeted for engineering students and should not be used for academic work purposes. Therefore, each registering user would be verified by RTLery site administration and users who cannot be verified as corporate or freelance users would unfortunately have to be rejected.

The RTLery website enables logic design and verification engineers to leverage knowledge available in the design community when coming to design logical components that are in wide use. The designer can use the site both as a learning tool where knowledge can be acquired, and as a reference design example serving to shorten the design and time. The components on the site are documented and verified, allowing simple reuse and fast integration. The code examples are open for modifications so you can adopt the design to your needs with minimal effort.

The benefits you get as a logic designer from using the site are the ability to expand the knowledge and design capabilities using examples of different designs and algorithms widely used in the industry. The code examples provide you with fast and safe implementation of the knowledge in your block. Using the available components allows you to concentrate on your block functionality and architectural requirements, rather than the details of implementing and debugging low level components.

The users of the site are design and verification engineers from design teams of medium and large fabless semiconductor companies, as well as design teams in startups, design service providers and freelancers. Practically all design engineers can use the site to speed up their design time while keeping the quality high and upgrading their knowledge.

Design teams can use the site as a library of pre-designed and pre-verified design components. the library is maintained and updated with the latest timing and verification requirements and can serve to reduce the variation of implementations across the team as well as preventing the risky "cut-modify-use" practice of code re-use within the design team. The library would have its own coding style so designs can be easily understood among the team members.

Components are generic pieces of code used widely in the semiconductor industry. Some examples of components would be FIFOs, synchronizers, clock dividers, arbitration algorithms, memory wrappers, lists, queues, counters, ECC blocks, PRBS, handshake protocols and many more. Those blocks can be found in many different semiconductor ASICs and SOCs.

The site contain many types of components, please see the menu on the front page or the above components drop-down on the main menu.

The components on the RTLery site were designed and verified by experienced design engineers under a very strict coding style and verification coverage guidelines.

The quality of a design component is always only as good as its verification planning and execution. The RTLery components are verified to a very high standard and you get a copy of the verification plan done for the component along with the downloaded information. The overall quality of you design would increase as typically when your block is verified as a whole, the level of details you would find in the verification plan would not be reached.

The components in the RTLery site are targeted at providing you valuable knowledge you can later apply in other designs and as such, must be properly documented. Understanding that not all applications are alike and every device has its own timing and layout conditions and constraints,  the RTLery components documentation is written for the purpose of facilitating changes to the code with minimal functional risk.

The RTLery components documentation contains a detailed list of assumptions regarding the external interfaces of the components and their respective logical behaviour and restrictions. This information should be used to check that the surrounding logic does not violate the component assumptions. The functionality you expect the component to perform should be verified in the context of your block environment where you can check that the component does its expected architectural function. It is your responsibility to make sure there is no mismatch between your expectation of the component functionality and its actual functionality in the context of your application!.

All RTLery components are written in Verilog. The verification environments which are a part of the download information would be written either in behavioural Verilog or SystemVerilog, depending on the component complexity.

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