Expert designer for ASIC top level, PLLs integration, clocking and reset schemes in few ASIC projects. Specialty in synthesis and STA tasks and in interfacing with external ASIC vendors, design preparation for physical design, floor-planning, constraints definition and DFT integration. project leader of design, verification and post-silicon validation teams under tight schedule in a variety of complex devices. Experience in VLSI project manager already led 2 chips all the way from specs to mass production. Experience with VLSI chip design flow: MicroArchitecture, RTL Coding, DFT insertion, IP Integration, Timing Closure, floor-planning and Physical Design, Lab System Validation and Production Testing Specialties: VLSI chip design project management from definition to validation DDR2, DDR3 physical interface (PHY) architecture, design, integration, timing with successfull implementation in two process nodes running up to 666Mhz (DDR-1333) complex chip design, verification, synthesis and timing.