RTLery participated in the project performing architectural exploration for power and performance, synthesis of blocks and full-chip, STA and timing reviews as well as floor planning, clock distribution logic and PLL integration.
The company develops devices for Bitcoin mining. The devices for the bitcoin market have very short life-cycle and their main focus is on power vs. performance tradeoffs. The purpose of the development is to reduce the power consumed per the device throughput thus maximizing the value of the device operation.
In the Architecture exploration phase RTLery’s role was to build and run a flow for power estimation of different architectural and design variations. The power estimation flow used the design compiler (DC) tool to generate an SDF cell delay format for each of the cells and nets of the design. The SDF is then used for simulating the design, generating a VCD file capturing the change to each node in the design. The VCD file node toggle information is used to produce activity information per node in the netlist. Once the activity information is available, DC can be used again in its power mode to generate a power report of the design. The power estimation flow enables swift and accurate power estimation in different voltage levels, library corners and design strategies, leading to the selection of the best suitable implementation. The flow was fully scripted and automated, making it very easy to analyze a large variety of options, different operation frequencies and library flavors.
For more detail about early power estimation see this post
DLL and clocking logic
The device high power consumption posts a significant challenge in handling both static and dynamic IR drop. The large number of computational blocks and the even power distribution over time results in high peak-power demand during the clock transition time. To reduce the peak power effect the best solution is a DLL. A digital DLL can be used for to shift each of the clocks going to the different blocks on the device by a constant portion of the clock, so if you want the clocks to be shifted by specific portion of the cycle, you can set the delay line accordingly for each of the blocks so when you change the frequency, the DLL will keep the same phase shift between the clocks for optimal peak power reduction. For more information about DLL usage for peak power reduction see this post
In addition to the DLL implementation and integration, RTLery designed the clocking and reset block of the device, integrating the PLL and designing the power-up control sequence logic. For more details about RTLery service for clock and reset see here
RTLery performed synthesis for the device computational block and top level integration, delivering the netlist to the ASIC vendor that implemented the chip.
Timing closure and Tape-Out review
At the final stage, RTLery performed the device signoff timing and STA verification based on extracted delays and participated in the layout review done prior to tapeout.