Psram memory controller development

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RTLery developed to specification a controller for PSRAM (Pseudo SRAM) memory including a verification environment, timing constraints and documentation.

Project overview

The company develops mobile devices for digital TV reception. The project is a complex SOC integrating modems, control logic and application interfaces. RTLery’s assignment was to develop a memory interface to a PSRAM memory used for storing video data. A PSRAM memory (Pseudo-SRAM) is actually a DRAM memory at low frequency where the overhead of managing the DRAM is done by the memory itself, so the exposed interface is similar to an SRAM memory interface.

Requirements definition

At this stage the requirements of the interface where defined, the actual operation modes that will be used and the required frequency and initialization sequence. The definition included a very robust timing for the external bus signals, allowing future connection of different SRAM devices.

Design and verification

The design phase included detailed design of the controller interface to the application logic and the signaling and data interface to the external memory bus. The verification effort included integration of memory models from several PSRAM memory vendors, a self-checking environment that uses backdoor memory access to pre-initialize the memory with known values and a detailed test plan.

Timing definitions

RTLery provided a detailed documented explanation of the requirements of the controller in terms of AC timing and facilitated the clocking structure by providing exact drawings of the clock sources and balancing requirements.


This project leverages RTLery’s capabilities in design of system and memory interfaces and its proven track record of memory interface design. The developed controller was fully functional, meeting timing and performance requirements.

For more details about RTLery’s PSRAM controller see here.

Client: Siano Mobile silicon
Time: 1 month