Soc architecture and design

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RTLery’s assignment in this project was to develop a robust SOC architecture based on customer requirements, perform power performance and area estimations, assist in IP selection and document the architecture for the design team to implement. RTLery also assisted in selecting an ASIC vendor for the project and defined power modes and power saving strategy for the device.

Project overview

The project is a video processing device for gaming application developed by one of the industry giants. The project was fully outsourced to a service provider that used RTLery for the architecture and design phase of the project. The device is a complex SOC with multiple DSP processors and a system controller CPU and includes several proprietary computational blocks as well as video interfaces and a large external DDR memory.

Architecture definition and IP selection

The process of architecture definition and IP selection for this project was dependent on the process selection and power envelope. The availability of the require IPs for system interfaces and internal DSP processors and the power estimation delivered by the vendor were essential in order to allow for the integration of the IP in the device. The task of power estimation under the different power consumption scenarios enabled the selection of IP, process and architectural structure.

Process selection

The process selection for this device was driven by the power envelope and the area budget of the device as well as the availability of specific interface IPs that were essential the tradeoffs for power and area pointed to 28nm process

PPA estimation

The task of evaluating power performance and area in an environment with high level of uncertainty, lack of clear definitions of the required performance and limited access to the intended operation scenarios of the device is very challenging. A correct power estimation is achieved by doing the correct assumptions regarding the predicted power of each of the design elements and refining the results as the project progresses.

Logic design

RTLery was assigned to design one of the main blocks of the device, integrating a large memory array, few DSP processors and additional computational blocks

Tasks performed by RTLery

RTLery performed and participated in the following tasks:




Architecture definition

Clocking requirement, clocking scheme

Power modes partitioning

DSP processors integration

DDR width and frequency according to performance

Main bus hierarchy and definition

Peripherals connectivity

Power-up, boot and initialization sequence

Block partitioning

IP selection

IP evaluation, questions to support, power information

IP connectivity checking

Area and power estimation for operation modes

Logic design

Micro-architecture and design of several blocks

Design reviews of other designers

PPA analysis

Power estimation spreadsheets for different modes

Integration of different IP power numbers

Cell count and area estimations

Estimation of physical design effects on design growth

ASIC vendors evaluation

Define questionnaire and evaluation criteria

Assessment of vendor capabilities

Handling information exchange


The task of defining an SOC architecture based on very little information is complex. RTLery’s experience and ability to use partial information to generate a good basis for decisions about IP purchases and backend targets proved to be essential in this case to the success of this project architecture. The project was eventually cancelled for reasons of budget.

Client: Veriest Ventures
Time: 5 months