Thermal camera device integration

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RTLery’s participation in the project included PLL instantiation, device integration, clock multiplexing and dividers, system interface design, constraints for synthesis and STA reviews

Project overview

The company develops thermal sensing devices for military and civilian uses and has a long track record in developing FPGA solutions and extensive knowhow in logic design of video processing algorithms. The ASIC is composed of multiple pipelined video processing computational blocks, memories for tables and frame storage, video-in and video-out interfaces. The chip is controlled from an external system controller interfacing through an asynchronous interface and a large FLASH for storage of configuration and calibration data. The device is implemented using 65nm process with moderate frequency requirements with a target to significantly reduce the power consumption, enabling the use of the device on mobile platforms. The physical implementation is done by an ASIC vendor in Shanghai, China.

Design and timing tasks

RTLery joined the project when all computational blocks where designed and the top level integration started. The following tasks were performed:

Task

description

Controller interface

Design of asynchronous controller interface block

Synchronization to internal clock

Integration with on-chip control and status bus

Control and status bus(CSR)

CSR bus master block

CSR slave to be placed in each functional block

Clock and reset

Initialization sequence for 3 PLLs

Reset propagation to device blocks

Clock dividers at required locations

Main clock divider for video level frequency

Clock switching for memory tables throughout the device

Integration of clock measurement components

Peripherals

Camera link interface implementation

QSPI Flash interface modification for AC timing

Timing constraints

Block and top  level constraints preparation

AC timing constraints

Constraints review for P&R stage

results review

Review of STA timing results

Review of floor-plan

Review of AC timing results.

Review of DFT specification and results.

Tape-out review with ASIC vendor

Gate level simulation

Support for gate-level simulation

debug of failures and X’s

Lab bring-up support

Support for initialization of device clocking and reset

 

Conclusions

This project leveraged RTLery’s main competencies into a successful Tape-out and first silicon product. RTLery’s methodology was used for all of the above tasks and proved to be a good solution for FPGA team going into ASIC design. The project also utilized many of RTLery components and core blocks.

Client: Senso-optics
Time: 7 months