Clock and reset logic design

clock and reset block diagram

Every ASIC device requires a power-up and clocking initialization sequence, enabling clock to start and reset to be propagated through to all parts of the logic. This sensitive logic is responsible for initializing the main device PLL and releases from reset the portions of the design that are required for booting the device.

The clocking and reset initialization sequence is different from other purely logical parts as it handles slow signals external to the device, an analog PLL and depends on the sequencing of the device power rails, external clock generators and I/O pads. In many cases, testability and initialization backup logic is also included, further complicating this delicate logic.

RTLery offers to design a complete clock and reset solution for an ASIC device according to the requirements and support the integration of the block through the different design stages for DFT insertion, timing definitions, I/O integration and STA. we can design the clocking and reset for any PLL specification and power-up sequences requirements.

The design service is based on a pre-designed component which is a simplified example of a device clocking and reset sequence and can be used as a reference and starting point for the implementation of this logic. The reference design contains the PLL startup logic, reset synchronization and propagation and handles clock selection and bypassing as well as reset distribution at the chip top level.

More details about the Chip clock and reset initialization reference design component.

The design of an ASIC clocking and reset logic is a sensitive task. Different PLLs require special attention in the initialization sequence and a design that is not robust enough to handle the situation may result in a device where the clocks cannot be used. The clocks and reset block includes multiple clock domain, specific layout requirements, externally driven signals as well as internal controls and other complications. In many cases multiple PLLs need to be initialized and a specific power-up order needs to be followed using a sequence that involves both hardware and software. The definition of the device reset sequence and reset distribution method is essential for securing a known state of all device IPs sequential elements. The clocks and reset block affects the device DFT, timing closure, ATE testing, bring-up and validation and a wide perspective is required to enable integration of all requirements into a robust design.

RTLery offers the following stages for development:

Stage

duration

details

definitions

1-2WW

Review of clocking requirements, specific PLL details

Review of overall power-up sequence and software/hardware partition

Review of reset requirements

Review of DFT clocking requirements

Definition of required configuration and source of information

Definition of initial solution

Initial design

1-2WW

Detailed documentation of the design for design review

Design and coding of the main functionality

Integration

1WW

Integrate the initial design into the device

Basic verification of the design

DFT

1WW

Add DFT requirements to the design

Verification

1WW

Define test items for the logic

Timing

1WW

Define timing requirements, clock balancing strategy

Document clocking instructions for physical design

Support

1-2WW

Modifications and late changes if needed

Gate level simulation support for power-up test

 

The design of a robust and low risk clocking and reset structure is essential for first time ASIC success. RTLery offers a vast experience and long track record of successful design of this sensitive logic.