Synthesis and sta

development flow

As more fabless chip design companies and system providers use ASIC implementation services, the need for expertize in synthesis and timing has grown significantly. The very success of the project relies of successful communication of the design intent to the implementation team using the language terms of ASIC place and route methodology. The correctness of the timing constraints delivered to the ASIC vendor has become an issue of high importance.

The design itself should be targeted for better timing closure by using proven design methodologies that reduce physical implementation risks and checking the RTL readiness for synthesis and physical design. Clear and simple definition of the clocking structure is essential for reducing the overdesign required for timing closure and preventing integration issues that appear late in the implementation design cycle.

RTLery offers help you in preparing your ASIC for backend flow and the requirements of ASIC implementation service providers. RTLery will prepare constraints, assist in synthesis, define floor-plan guidelines and review results. Interfacing to external ASIC vendor may be difficult if you do not have the capabilities to communicate your requirement in a technical level that is understood by your ASIC vendor’s engineers.

Your device RTL should be ready for backend in terms of inter-block interfaces, timing definitions, clock distribution, reset method, top level I/O connectivity, AC timing constraints, DFT and block partitioning. Failing to meet the basic needs of the vendor in any of those areas would lead to repeated work, delays and poor results. We will help you prepare for meeting the vendor requirements, review RTL status and propose ways to facilitate easier interaction with the vendor, help you fix the design per the vendor requirements and assist in evaluating the results of the vendor’s work in terms of timing results.

The importance of performing STA locally by your team is very high, allowing for independent testing of the results in a separate environment where you can be sure the constraints are set correctly to cover special paths and other exceptions. RTLery has the methodology and experience to build a complete timing verification environment that will give you the required confidence that the physical implementation phase follows the design guidelines and constraints.

RTLery proposes to perform or assist in the following tasks:

Task name

Description

RTL preparation review

Inter-block connectivity

Clocking structure, CDC, clock gating, clock dividers

Power domain separation

Connectivity to I/O

Reset propagation, soft reset

Constraints preparation

Define block level constraints

Review multi-cycle paths

Review IP connectivity and integrate IP constraints

Define AC timing per interface

Define top level constraints for functional modes and DFT mode

Synthesis

TCL scripting environment for synthesis flow

Implementation of special timing checks

Reporting of PPA parameters and timing results

Formal equivalence checking

Preparation for physical design

Define floor-plan and physical block partitioning

Document clocking structure and balancing requirements

Define pad placement, PLL location, interface IP location

Preparation for STA

Build STA environment, TCL scripting, AC timing checks, DCD checks

Timing and P&R debug

Debug timing reports, congestion reports, AC timing results

Perform STA

Check timing results of post-layout

Perform special timing checks and AC timing

Check different modes of operation, including DFT

Using RTLery’s expertise for bridging the gap between the logic design team and the ASIC vendor proved to be the right choice for our customers. See more details about our recent projects here.